Subzero. ARM32. Folding rematerializable offsets in address operands.

src/IceTargetLoweringARM32.h

 //===- subzero/src/IceTargetLoweringARM32.h - ARM32 lowering ----*- C++ -*-===//
 //
 //                        The Subzero Code Generator
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 ///
 /// \file
@@ skipping 72 matching lines @@
   const llvm::SmallBitVector &getAliasesForRegister(SizeT Reg) const override {
     return RegisterAliases[Reg];
   }
   bool hasFramePointer() const override { return UsesFramePointer; }
   void setHasFramePointer() override { UsesFramePointer = true; }
   SizeT getStackReg() const override { return RegARM32::Reg_sp; }
   SizeT getFrameReg() const override { return RegARM32::Reg_fp; }
   SizeT getFrameOrStackReg() const override {
     return UsesFramePointer ? getFrameReg() : getStackReg();
   }
-  SizeT getReservedTmpReg() const { return RegARM32::Reg_ip; }
+  int32_t getReservedTmpReg() const { return RegARM32::Reg_ip; }
 
   size_t typeWidthInBytesOnStack(Type Ty) const override {
     // Round up to the next multiple of 4 bytes. In particular, i1, i8, and i16
     // are rounded up to 4 bytes.
     return (typeWidthInBytes(Ty) + 3) & ~3;
   }
   uint32_t getStackAlignment() const override;
   void reserveFixedAllocaArea(size_t Size, size_t Align) override {
     FixedAllocaSizeBytes = Size;
     assert(llvm::isPowerOf2_32(Align));
@@ skipping 30 matching lines @@
   Operand *loOperand(Operand *Operand);
   Operand *hiOperand(Operand *Operand);
   void finishArgumentLowering(Variable *Arg, Variable *FramePtr,
                               size_t BasicFrameOffset, size_t *InArgsSizeBytes);
 
   bool hasCPUFeature(TargetARM32Features::ARM32InstructionSet I) const {
     return CPUFeatures.hasFeature(I);
   }
 
   enum OperandLegalization {
-    Legal_None = 0,
     Legal_Reg = 1 << 0,  /// physical register, not stack location
     Legal_Flex = 1 << 1, /// A flexible operand2, which can hold rotated small
                          /// immediates, shifted registers, or modified fp imm.
     Legal_Mem = 1 << 2,  /// includes [r0, r1 lsl #2] as well as [sp, #12]
-    Legal_All = ~Legal_None
+    Legal_Rematerializable = 1 << 3,
+    Legal_All = ~Legal_Rematerializable,
   };
 
   using LegalMask = uint32_t;
   Operand *legalizeUndef(Operand *From, int32_t RegNum = Variable::NoRegister);
   Operand *legalize(Operand *From, LegalMask Allowed = Legal_All,
                     int32_t RegNum = Variable::NoRegister);
   Variable *legalizeToReg(Operand *From, int32_t RegNum = Variable::NoRegister);
 
   OperandARM32ShAmtImm *shAmtImm(uint32_t ShAmtImm) const {
     assert(ShAmtImm < 32);
@@ skipping 649 matching lines @@
     Context.insert(InstARM32Vsub::create(Func, Dest, Src0, Src1));
   }
 
   // Iterates over the CFG and determines the maximum outgoing stack arguments
   // bytes. This information is later used during addProlog() to pre-allocate
   // the outargs area.
   // TODO(jpp): This could live in the Parser, if we provided a Target-specific
   // method that the Parser could call.
   void findMaxStackOutArgsSize();
 
-  /// Run a pass through stack variables and ensure that the offsets are legal.
-  /// If the offset is not legal, use a new base register that accounts for the
-  /// offset, such that the addressing mode offset bits are now legal.
-  void legalizeStackSlots();
-  /// Returns true if the given Offset can be represented in a ldr/str.
+  /// Returns true if the given Offset can be represented in a Load/Store Mem
+  /// Operand.
   bool isLegalMemOffset(Type Ty, int32_t Offset) const;
-  // Creates a new Base register centered around
-  // [OrigBaseReg, +/- Offset].
-  Variable *newBaseRegister(int32_t Offset, Variable *OrigBaseReg);
-  /// Creates a new, legal OperandARM32Mem for accessing OrigBase + Offset. The
-  /// returned mem operand is a legal operand for accessing memory that is of
-  /// type Ty.
-  ///
-  /// If [OrigBaseReg, #Offset] is encodable, then the method returns a Mem
-  /// operand expressing it. Otherwise,
-  ///
-  /// if [*NewBaseReg, #Offset-*NewBaseOffset] is encodable, the method will
-  /// return that. Otherwise,
-  ///
-  /// a new base register ip=OrigBaseReg+Offset is created, and the method
-  /// returns [ip, #0].
-  OperandARM32Mem *createMemOperand(Type Ty, int32_t Offset,
-                                    Variable *OrigBaseReg,
-                                    Variable **NewBaseReg,
-                                    int32_t *NewBaseOffset);
-  /// Legalizes Mov if its Source (or Destination) is a spilled Variable. Moves
-  /// to memory become store instructions, and moves from memory, loads.
-  void legalizeMov(InstARM32Mov *Mov, Variable *OrigBaseReg,
-                   Variable **NewBaseReg, int32_t *NewBaseOffset);
+
+  void postLowerLegalization();
+
+  class PostLoweringLegalizer {
+    PostLoweringLegalizer() = delete;
+    PostLoweringLegalizer(const PostLoweringLegalizer &) = delete;
+    PostLoweringLegalizer &operator=(const PostLoweringLegalizer &) = delete;
+
+  public:
+    explicit PostLoweringLegalizer(TargetARM32 *Target)
+        : Target(Target), StackOrFrameReg(Target->getPhysicalRegister(
+                              Target->getFrameOrStackReg())) {}
+
+    void resetTempBaseIfClobberedBy(const Inst *Instr);
+
+    // Ensures that the TempBase register held by the this legalizer (if any) is
+    // assigned to IP.
+    void assertNoTempOrAssignedToIP() const {
+      assert(TempBaseReg == nullptr ||
+             TempBaseReg->getRegNum() == Target->getReservedTmpReg());
+    }
+
+    // Legalizes Mem. if Mem.Base is a Reamaterializable variable, Mem.Offset is
+    // fixed up.
+    OperandARM32Mem *legalizeMemOperand(OperandARM32Mem *Mem,
+                                        bool AllowOffsets = true);
+
+    /// Legalizes Mov if its Source (or Destination) is a spilled Variable, or
+    /// if its Source is a Rematerializable variable (this form is used in lieu
+    /// of lea, which is not available in ARM.)
+    ///
+    /// Moves to memory become store instructions, and moves from memory, loads.
+    void legalizeMov(InstARM32Mov *Mov);
+
+  private:
+    /// Creates a new Base register centered around [Base, +/- Offset].
+    Variable *newBaseRegister(Variable *Base, int32_t Offset,
+                              int32_t ScratchRegNum);
+
+    /// Creates a new, legal OperandARM32Mem for accessing Base + Offset.
+    /// The returned mem operand is a legal operand for accessing memory that is
+    /// of type Ty.
+    ///
+    /// If [Base, #Offset] is encodable, then the method returns a Mem operand
+    /// expressing it. Otherwise,
+    ///
+    /// if [TempBaseReg, #Offset-TempBaseOffset] is a valid memory operand, the
+    /// method will return that. Otherwise,
+    ///
+    /// a new base register ip=Base+Offset is created, and the method returns a
+    /// memory operand expressing [ip, #0].
+    OperandARM32Mem *createMemOperand(Type Ty, Variable *Base, int32_t Offset,
+                                      bool AllowOffsets = true);
+    TargetARM32 *const Target;
+    Variable *const StackOrFrameReg;
+    Variable *TempBaseReg = nullptr;
+    int32_t TempBaseOffset = 0;
+  };
 
   TargetARM32Features CPUFeatures;
   bool UsesFramePointer = false;
   bool NeedsStackAlignment = false;
   bool MaybeLeafFunc = true;
   size_t SpillAreaSizeBytes = 0;
   size_t FixedAllocaSizeBytes = 0;
   size_t FixedAllocaAlignBytes = 0;
   bool PrologEmitsFixedAllocas = false;
   uint32_t MaxOutArgsSizeBytes = 0;
@@ skipping 186 matching lines @@
 
 private:
   ~TargetHeaderARM32() = default;
 
   TargetARM32Features CPUFeatures;
 };
 
 } // end of namespace Ice
 
 #endif // SUBZERO_SRC_ICETARGETLOWERINGARM32_H