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Side by Side Diff: src/compiler/arm/instruction-codes-arm.h

Issue 1477753002: [turbofan] Implemented the optional Float32RoundTiesEven operator. (Closed) Base URL: https://chromium.googlesource.com/v8/v8.git@f32trunc
Patch Set: Merging with the changed codebase Created 5 years ago
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1 // Copyright 2014 the V8 project authors. All rights reserved. 1 // Copyright 2014 the V8 project authors. All rights reserved.
2 // Use of this source code is governed by a BSD-style license that can be 2 // Use of this source code is governed by a BSD-style license that can be
3 // found in the LICENSE file. 3 // found in the LICENSE file.
4 4
5 #ifndef V8_COMPILER_ARM_INSTRUCTION_CODES_ARM_H_ 5 #ifndef V8_COMPILER_ARM_INSTRUCTION_CODES_ARM_H_
6 #define V8_COMPILER_ARM_INSTRUCTION_CODES_ARM_H_ 6 #define V8_COMPILER_ARM_INSTRUCTION_CODES_ARM_H_
7 7
8 namespace v8 { 8 namespace v8 {
9 namespace internal { 9 namespace internal {
10 namespace compiler { 10 namespace compiler {
(...skipping 54 matching lines...) Expand 10 before | Expand all | Expand 10 after
65 V(ArmVabsF64) \ 65 V(ArmVabsF64) \
66 V(ArmVnegF64) \ 66 V(ArmVnegF64) \
67 V(ArmVsqrtF64) \ 67 V(ArmVsqrtF64) \
68 V(ArmVrintmF32) \ 68 V(ArmVrintmF32) \
69 V(ArmVrintmF64) \ 69 V(ArmVrintmF64) \
70 V(ArmVrintpF32) \ 70 V(ArmVrintpF32) \
71 V(ArmVrintpF64) \ 71 V(ArmVrintpF64) \
72 V(ArmVrintzF32) \ 72 V(ArmVrintzF32) \
73 V(ArmVrintzF64) \ 73 V(ArmVrintzF64) \
74 V(ArmVrintaF64) \ 74 V(ArmVrintaF64) \
75 V(ArmVrintnF32) \
75 V(ArmVrintnF64) \ 76 V(ArmVrintnF64) \
76 V(ArmVcvtF32F64) \ 77 V(ArmVcvtF32F64) \
77 V(ArmVcvtF64F32) \ 78 V(ArmVcvtF64F32) \
78 V(ArmVcvtF64S32) \ 79 V(ArmVcvtF64S32) \
79 V(ArmVcvtF64U32) \ 80 V(ArmVcvtF64U32) \
80 V(ArmVcvtS32F64) \ 81 V(ArmVcvtS32F64) \
81 V(ArmVcvtU32F64) \ 82 V(ArmVcvtU32F64) \
82 V(ArmVmovLowU32F64) \ 83 V(ArmVmovLowU32F64) \
83 V(ArmVmovLowF64U32) \ 84 V(ArmVmovLowF64U32) \
84 V(ArmVmovHighU32F64) \ 85 V(ArmVmovHighU32F64) \
(...skipping 31 matching lines...) Expand 10 before | Expand all | Expand 10 after
116 V(Operand2_R_ASR_R) /* %r0 ASR %r1 */ \ 117 V(Operand2_R_ASR_R) /* %r0 ASR %r1 */ \
117 V(Operand2_R_LSL_R) /* %r0 LSL %r1 */ \ 118 V(Operand2_R_LSL_R) /* %r0 LSL %r1 */ \
118 V(Operand2_R_LSR_R) /* %r0 LSR %r1 */ \ 119 V(Operand2_R_LSR_R) /* %r0 LSR %r1 */ \
119 V(Operand2_R_ROR_R) /* %r0 ROR %r1 */ 120 V(Operand2_R_ROR_R) /* %r0 ROR %r1 */
120 121
121 } // namespace compiler 122 } // namespace compiler
122 } // namespace internal 123 } // namespace internal
123 } // namespace v8 124 } // namespace v8
124 125
125 #endif // V8_COMPILER_ARM_INSTRUCTION_CODES_ARM_H_ 126 #endif // V8_COMPILER_ARM_INSTRUCTION_CODES_ARM_H_
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