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1 // Copyright 2014 the V8 project authors. All rights reserved. | 1 // Copyright 2014 the V8 project authors. All rights reserved. |
2 // Use of this source code is governed by a BSD-style license that can be | 2 // Use of this source code is governed by a BSD-style license that can be |
3 // found in the LICENSE file. | 3 // found in the LICENSE file. |
4 | 4 |
5 #ifndef V8_COMPILER_MIPS_INSTRUCTION_CODES_MIPS_H_ | 5 #ifndef V8_COMPILER_MIPS_INSTRUCTION_CODES_MIPS_H_ |
6 #define V8_COMPILER_MIPS_INSTRUCTION_CODES_MIPS_H_ | 6 #define V8_COMPILER_MIPS_INSTRUCTION_CODES_MIPS_H_ |
7 | 7 |
8 namespace v8 { | 8 namespace v8 { |
9 namespace internal { | 9 namespace internal { |
10 namespace compiler { | 10 namespace compiler { |
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65 V(Mips64DivD) \ | 65 V(Mips64DivD) \ |
66 V(Mips64ModD) \ | 66 V(Mips64ModD) \ |
67 V(Mips64AbsD) \ | 67 V(Mips64AbsD) \ |
68 V(Mips64SqrtD) \ | 68 V(Mips64SqrtD) \ |
69 V(Mips64MaxD) \ | 69 V(Mips64MaxD) \ |
70 V(Mips64MinD) \ | 70 V(Mips64MinD) \ |
71 V(Mips64Float64RoundDown) \ | 71 V(Mips64Float64RoundDown) \ |
72 V(Mips64Float64RoundTruncate) \ | 72 V(Mips64Float64RoundTruncate) \ |
73 V(Mips64Float64RoundUp) \ | 73 V(Mips64Float64RoundUp) \ |
74 V(Mips64Float64RoundTiesEven) \ | 74 V(Mips64Float64RoundTiesEven) \ |
| 75 V(Mips64Float32RoundDown) \ |
| 76 V(Mips64Float32RoundTruncate) \ |
| 77 V(Mips64Float32RoundUp) \ |
| 78 V(Mips64Float32RoundTiesEven) \ |
75 V(Mips64CvtSD) \ | 79 V(Mips64CvtSD) \ |
76 V(Mips64CvtDS) \ | 80 V(Mips64CvtDS) \ |
77 V(Mips64TruncWD) \ | 81 V(Mips64TruncWD) \ |
78 V(Mips64TruncLD) \ | 82 V(Mips64TruncLD) \ |
79 V(Mips64TruncUwD) \ | 83 V(Mips64TruncUwD) \ |
80 V(Mips64TruncUlD) \ | 84 V(Mips64TruncUlD) \ |
81 V(Mips64CvtDW) \ | 85 V(Mips64CvtDW) \ |
82 V(Mips64CvtSL) \ | 86 V(Mips64CvtSL) \ |
83 V(Mips64CvtSUl) \ | 87 V(Mips64CvtSUl) \ |
84 V(Mips64CvtDL) \ | 88 V(Mips64CvtDL) \ |
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130 #define TARGET_ADDRESSING_MODE_LIST(V) \ | 134 #define TARGET_ADDRESSING_MODE_LIST(V) \ |
131 V(MRI) /* [%r0 + K] */ \ | 135 V(MRI) /* [%r0 + K] */ \ |
132 V(MRR) /* [%r0 + %r1] */ | 136 V(MRR) /* [%r0 + %r1] */ |
133 | 137 |
134 | 138 |
135 } // namespace compiler | 139 } // namespace compiler |
136 } // namespace internal | 140 } // namespace internal |
137 } // namespace v8 | 141 } // namespace v8 |
138 | 142 |
139 #endif // V8_COMPILER_MIPS_INSTRUCTION_CODES_MIPS_H_ | 143 #endif // V8_COMPILER_MIPS_INSTRUCTION_CODES_MIPS_H_ |
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