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Side by Side Diff: src/compiler/mips/instruction-codes-mips.h

Issue 1477043004: MIPS: [turbofan] Implement Float32Round(TiesEven|RoundUp|RoundDown|Truncate). (Closed) Base URL: https://chromium.googlesource.com/v8/v8.git@master
Patch Set: Created 5 years ago
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1 // Copyright 2014 the V8 project authors. All rights reserved. 1 // Copyright 2014 the V8 project authors. All rights reserved.
2 // Use of this source code is governed by a BSD-style license that can be 2 // Use of this source code is governed by a BSD-style license that can be
3 // found in the LICENSE file. 3 // found in the LICENSE file.
4 4
5 #ifndef V8_COMPILER_MIPS_INSTRUCTION_CODES_MIPS_H_ 5 #ifndef V8_COMPILER_MIPS_INSTRUCTION_CODES_MIPS_H_
6 #define V8_COMPILER_MIPS_INSTRUCTION_CODES_MIPS_H_ 6 #define V8_COMPILER_MIPS_INSTRUCTION_CODES_MIPS_H_
7 7
8 namespace v8 { 8 namespace v8 {
9 namespace internal { 9 namespace internal {
10 namespace compiler { 10 namespace compiler {
(...skipping 38 matching lines...) Expand 10 before | Expand all | Expand 10 after
49 V(MipsCmpD) \ 49 V(MipsCmpD) \
50 V(MipsAddD) \ 50 V(MipsAddD) \
51 V(MipsSubD) \ 51 V(MipsSubD) \
52 V(MipsMulD) \ 52 V(MipsMulD) \
53 V(MipsDivD) \ 53 V(MipsDivD) \
54 V(MipsModD) \ 54 V(MipsModD) \
55 V(MipsAbsD) \ 55 V(MipsAbsD) \
56 V(MipsSqrtD) \ 56 V(MipsSqrtD) \
57 V(MipsMaxD) \ 57 V(MipsMaxD) \
58 V(MipsMinD) \ 58 V(MipsMinD) \
59 V(MipsFloat32RoundDown) \
60 V(MipsFloat32RoundTruncate) \
61 V(MipsFloat32RoundUp) \
62 V(MipsFloat32RoundTiesEven) \
59 V(MipsFloat64RoundDown) \ 63 V(MipsFloat64RoundDown) \
60 V(MipsFloat64RoundTruncate) \ 64 V(MipsFloat64RoundTruncate) \
61 V(MipsFloat64RoundUp) \ 65 V(MipsFloat64RoundUp) \
62 V(MipsFloat64RoundTiesEven) \ 66 V(MipsFloat64RoundTiesEven) \
63 V(MipsCvtSD) \ 67 V(MipsCvtSD) \
64 V(MipsCvtDS) \ 68 V(MipsCvtDS) \
65 V(MipsTruncWD) \ 69 V(MipsTruncWD) \
66 V(MipsTruncUwD) \ 70 V(MipsTruncUwD) \
67 V(MipsCvtDW) \ 71 V(MipsCvtDW) \
68 V(MipsCvtDUw) \ 72 V(MipsCvtDUw) \
(...skipping 39 matching lines...) Expand 10 before | Expand all | Expand 10 after
108 #define TARGET_ADDRESSING_MODE_LIST(V) \ 112 #define TARGET_ADDRESSING_MODE_LIST(V) \
109 V(MRI) /* [%r0 + K] */ \ 113 V(MRI) /* [%r0 + K] */ \
110 V(MRR) /* [%r0 + %r1] */ 114 V(MRR) /* [%r0 + %r1] */
111 115
112 116
113 } // namespace compiler 117 } // namespace compiler
114 } // namespace internal 118 } // namespace internal
115 } // namespace v8 119 } // namespace v8
116 120
117 #endif // V8_COMPILER_MIPS_INSTRUCTION_CODES_MIPS_H_ 121 #endif // V8_COMPILER_MIPS_INSTRUCTION_CODES_MIPS_H_
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