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1 // Copyright (c) 1994-2006 Sun Microsystems Inc. | 1 // Copyright (c) 1994-2006 Sun Microsystems Inc. |
2 // All Rights Reserved. | 2 // All Rights Reserved. |
3 // | 3 // |
4 // Redistribution and use in source and binary forms, with or without | 4 // Redistribution and use in source and binary forms, with or without |
5 // modification, are permitted provided that the following conditions | 5 // modification, are permitted provided that the following conditions |
6 // are met: | 6 // are met: |
7 // | 7 // |
8 // - Redistributions of source code must retain the above copyright notice, | 8 // - Redistributions of source code must retain the above copyright notice, |
9 // this list of conditions and the following disclaimer. | 9 // this list of conditions and the following disclaimer. |
10 // | 10 // |
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3383 DCHECK(CpuFeatures::IsSupported(ARMv8)); | 3383 DCHECK(CpuFeatures::IsSupported(ARMv8)); |
3384 int vd, d; | 3384 int vd, d; |
3385 dst.split_code(&vd, &d); | 3385 dst.split_code(&vd, &d); |
3386 int vm, m; | 3386 int vm, m; |
3387 src.split_code(&vm, &m); | 3387 src.split_code(&vm, &m); |
3388 emit(kSpecialCondition | 0x1D * B23 | d * B22 | 0x3 * B20 | B19 | 0x1 * B16 | | 3388 emit(kSpecialCondition | 0x1D * B23 | d * B22 | 0x3 * B20 | B19 | 0x1 * B16 | |
3389 vd * B12 | 0x5 * B9 | B8 | B6 | m * B5 | vm); | 3389 vd * B12 | 0x5 * B9 | B8 | B6 | m * B5 | vm); |
3390 } | 3390 } |
3391 | 3391 |
3392 | 3392 |
| 3393 void Assembler::vrintp(const SwVfpRegister dst, const SwVfpRegister src) { |
| 3394 // cond=kSpecialCondition(31-28) | 11101(27-23)| D(22) | 11(21-20) | |
| 3395 // 10(19-18) | RM=10(17-16) | Vd(15-12) | 101(11-9) | sz=0(8) | 01(7-6) | |
| 3396 // M(5) | 0(4) | Vm(3-0) |
| 3397 DCHECK(CpuFeatures::IsSupported(ARMv8)); |
| 3398 int vd, d; |
| 3399 dst.split_code(&vd, &d); |
| 3400 int vm, m; |
| 3401 src.split_code(&vm, &m); |
| 3402 emit(kSpecialCondition | 0x1D * B23 | d * B22 | 0x3 * B20 | B19 | 0x2 * B16 | |
| 3403 vd * B12 | 0x5 * B9 | B6 | m * B5 | vm); |
| 3404 } |
| 3405 |
| 3406 |
3393 void Assembler::vrintp(const DwVfpRegister dst, const DwVfpRegister src) { | 3407 void Assembler::vrintp(const DwVfpRegister dst, const DwVfpRegister src) { |
3394 // cond=kSpecialCondition(31-28) | 11101(27-23)| D(22) | 11(21-20) | | 3408 // cond=kSpecialCondition(31-28) | 11101(27-23)| D(22) | 11(21-20) | |
3395 // 10(19-18) | RM=10(17-16) | Vd(15-12) | 101(11-9) | sz=1(8) | 01(7-6) | | 3409 // 10(19-18) | RM=10(17-16) | Vd(15-12) | 101(11-9) | sz=1(8) | 01(7-6) | |
3396 // M(5) | 0(4) | Vm(3-0) | 3410 // M(5) | 0(4) | Vm(3-0) |
3397 DCHECK(CpuFeatures::IsSupported(ARMv8)); | 3411 DCHECK(CpuFeatures::IsSupported(ARMv8)); |
3398 int vd, d; | 3412 int vd, d; |
3399 dst.split_code(&vd, &d); | 3413 dst.split_code(&vd, &d); |
3400 int vm, m; | 3414 int vm, m; |
3401 src.split_code(&vm, &m); | 3415 src.split_code(&vm, &m); |
3402 emit(kSpecialCondition | 0x1D * B23 | d * B22 | 0x3 * B20 | B19 | 0x2 * B16 | | 3416 emit(kSpecialCondition | 0x1D * B23 | d * B22 | 0x3 * B20 | B19 | 0x2 * B16 | |
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4053 DCHECK(is_uint12(offset)); | 4067 DCHECK(is_uint12(offset)); |
4054 instr_at_put(pc, SetLdrRegisterImmediateOffset(instr, offset)); | 4068 instr_at_put(pc, SetLdrRegisterImmediateOffset(instr, offset)); |
4055 } | 4069 } |
4056 } | 4070 } |
4057 | 4071 |
4058 | 4072 |
4059 } // namespace internal | 4073 } // namespace internal |
4060 } // namespace v8 | 4074 } // namespace v8 |
4061 | 4075 |
4062 #endif // V8_TARGET_ARCH_ARM | 4076 #endif // V8_TARGET_ARCH_ARM |
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