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| 1 //===- subzero/src/IceTargetLoweringARM32.h - ARM32 lowering ----*- C++ -*-===// | 1 //===- subzero/src/IceTargetLoweringARM32.h - ARM32 lowering ----*- C++ -*-===// |
| 2 // | 2 // |
| 3 // The Subzero Code Generator | 3 // The Subzero Code Generator |
| 4 // | 4 // |
| 5 // This file is distributed under the University of Illinois Open Source | 5 // This file is distributed under the University of Illinois Open Source |
| 6 // License. See LICENSE.TXT for details. | 6 // License. See LICENSE.TXT for details. |
| 7 // | 7 // |
| 8 //===----------------------------------------------------------------------===// | 8 //===----------------------------------------------------------------------===// |
| 9 /// | 9 /// |
| 10 /// \file | 10 /// \file |
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| 230 void lowerInsertElement(const InstInsertElement *Inst) override; | 230 void lowerInsertElement(const InstInsertElement *Inst) override; |
| 231 void lowerLoad(const InstLoad *Inst) override; | 231 void lowerLoad(const InstLoad *Inst) override; |
| 232 void lowerPhi(const InstPhi *Inst) override; | 232 void lowerPhi(const InstPhi *Inst) override; |
| 233 void lowerRet(const InstRet *Inst) override; | 233 void lowerRet(const InstRet *Inst) override; |
| 234 void lowerSelect(const InstSelect *Inst) override; | 234 void lowerSelect(const InstSelect *Inst) override; |
| 235 void lowerStore(const InstStore *Inst) override; | 235 void lowerStore(const InstStore *Inst) override; |
| 236 void lowerSwitch(const InstSwitch *Inst) override; | 236 void lowerSwitch(const InstSwitch *Inst) override; |
| 237 void lowerUnreachable(const InstUnreachable *Inst) override; | 237 void lowerUnreachable(const InstUnreachable *Inst) override; |
| 238 void prelowerPhis() override; | 238 void prelowerPhis() override; |
| 239 uint32_t getCallStackArgumentsSizeBytes(const InstCall *Instr) override; | 239 uint32_t getCallStackArgumentsSizeBytes(const InstCall *Instr) override; |
| 240 void genTargetHelperCallFor(Inst *Instr) override { (void)Instr; } | 240 void genTargetHelperCallFor(Inst *Instr) override; |
| 241 void doAddressOptLoad() override; | 241 void doAddressOptLoad() override; |
| 242 void doAddressOptStore() override; | 242 void doAddressOptStore() override; |
| 243 void randomlyInsertNop(float Probability, | 243 void randomlyInsertNop(float Probability, |
| 244 RandomNumberGenerator &RNG) override; | 244 RandomNumberGenerator &RNG) override; |
| 245 | 245 |
| 246 OperandARM32Mem *formMemoryOperand(Operand *Ptr, Type Ty); | 246 OperandARM32Mem *formMemoryOperand(Operand *Ptr, Type Ty); |
| 247 | 247 |
| 248 Variable64On32 *makeI64RegPair(); | 248 Variable64On32 *makeI64RegPair(); |
| 249 Variable *makeReg(Type Ty, int32_t RegNum = Variable::NoRegister); | 249 Variable *makeReg(Type Ty, int32_t RegNum = Variable::NoRegister); |
| 250 static Type stackSlotType(); | 250 static Type stackSlotType(); |
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| 261 uint64_t Salt) const override; | 261 uint64_t Salt) const override; |
| 262 | 262 |
| 263 // If a divide-by-zero check is needed, inserts a: test; branch .LSKIP; trap; | 263 // If a divide-by-zero check is needed, inserts a: test; branch .LSKIP; trap; |
| 264 // .LSKIP: <continuation>. If no check is needed nothing is inserted. | 264 // .LSKIP: <continuation>. If no check is needed nothing is inserted. |
| 265 void div0Check(Type Ty, Operand *SrcLo, Operand *SrcHi); | 265 void div0Check(Type Ty, Operand *SrcLo, Operand *SrcHi); |
| 266 using ExtInstr = void (TargetARM32::*)(Variable *, Variable *, | 266 using ExtInstr = void (TargetARM32::*)(Variable *, Variable *, |
| 267 CondARM32::Cond); | 267 CondARM32::Cond); |
| 268 using DivInstr = void (TargetARM32::*)(Variable *, Variable *, Variable *, | 268 using DivInstr = void (TargetARM32::*)(Variable *, Variable *, Variable *, |
| 269 CondARM32::Cond); | 269 CondARM32::Cond); |
| 270 void lowerIDivRem(Variable *Dest, Variable *T, Variable *Src0R, Operand *Src1, | 270 void lowerIDivRem(Variable *Dest, Variable *T, Variable *Src0R, Operand *Src1, |
| 271 ExtInstr ExtFunc, DivInstr DivFunc, | 271 ExtInstr ExtFunc, DivInstr DivFunc, bool IsRemainder); |
| 272 const char *DivHelperName, bool IsRemainder); | |
| 273 | 272 |
| 274 void lowerCLZ(Variable *Dest, Variable *ValLo, Variable *ValHi); | 273 void lowerCLZ(Variable *Dest, Variable *ValLo, Variable *ValHi); |
| 275 | 274 |
| 276 // The following are helpers that insert lowered ARM32 instructions with | 275 // The following are helpers that insert lowered ARM32 instructions with |
| 277 // minimal syntactic overhead, so that the lowering code can look as close to | 276 // minimal syntactic overhead, so that the lowering code can look as close to |
| 278 // assembly as practical. | 277 // assembly as practical. |
| 279 void _add(Variable *Dest, Variable *Src0, Operand *Src1, | 278 void _add(Variable *Dest, Variable *Src0, Operand *Src1, |
| 280 CondARM32::Cond Pred = CondARM32::AL) { | 279 CondARM32::Cond Pred = CondARM32::AL) { |
| 281 Context.insert(InstARM32Add::create(Func, Dest, Src0, Src1, Pred)); | 280 Context.insert(InstARM32Add::create(Func, Dest, Src0, Src1, Pred)); |
| 282 } | 281 } |
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| 910 llvm::SmallBitVector ValidF64Regs; | 909 llvm::SmallBitVector ValidF64Regs; |
| 911 llvm::SmallBitVector ValidV128Regs; | 910 llvm::SmallBitVector ValidV128Regs; |
| 912 }; | 911 }; |
| 913 | 912 |
| 914 private: | 913 private: |
| 915 ~TargetARM32() override = default; | 914 ~TargetARM32() override = default; |
| 916 | 915 |
| 917 OperandARM32Mem *formAddressingMode(Type Ty, Cfg *Func, const Inst *LdSt, | 916 OperandARM32Mem *formAddressingMode(Type Ty, Cfg *Func, const Inst *LdSt, |
| 918 Operand *Base); | 917 Operand *Base); |
| 919 | 918 |
| 919 void postambleCtpop64(const InstCall *Instr); |
| 920 void preambleDivRem(const InstCall *Instr); |
| 921 std::unordered_map<Operand *, void (TargetARM32::*)(const InstCall *Inst)> |
| 922 ARM32HelpersPreamble; |
| 923 std::unordered_map<Operand *, void (TargetARM32::*)(const InstCall *Inst)> |
| 924 ARM32HelpersPostamble; |
| 925 |
| 920 class BoolComputationTracker { | 926 class BoolComputationTracker { |
| 921 public: | 927 public: |
| 922 BoolComputationTracker() = default; | 928 BoolComputationTracker() = default; |
| 923 ~BoolComputationTracker() = default; | 929 ~BoolComputationTracker() = default; |
| 924 | 930 |
| 925 void forgetProducers() { KnownComputations.clear(); } | 931 void forgetProducers() { KnownComputations.clear(); } |
| 926 void recordProducers(CfgNode *Node); | 932 void recordProducers(CfgNode *Node); |
| 927 | 933 |
| 928 const Inst *getProducerOf(const Operand *Opnd) const { | 934 const Inst *getProducerOf(const Operand *Opnd) const { |
| 929 auto *Var = llvm::dyn_cast<Variable>(Opnd); | 935 auto *Var = llvm::dyn_cast<Variable>(Opnd); |
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| 1038 | 1044 |
| 1039 private: | 1045 private: |
| 1040 ~TargetHeaderARM32() = default; | 1046 ~TargetHeaderARM32() = default; |
| 1041 | 1047 |
| 1042 TargetARM32Features CPUFeatures; | 1048 TargetARM32Features CPUFeatures; |
| 1043 }; | 1049 }; |
| 1044 | 1050 |
| 1045 } // end of namespace Ice | 1051 } // end of namespace Ice |
| 1046 | 1052 |
| 1047 #endif // SUBZERO_SRC_ICETARGETLOWERINGARM32_H | 1053 #endif // SUBZERO_SRC_ICETARGETLOWERINGARM32_H |
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