Subzero. ARM32. Pre-lowers calls to ARM32 Helpers.

src/IceTargetLoweringARM32.h

 //===- subzero/src/IceTargetLoweringARM32.h - ARM32 lowering ----*- C++ -*-===//
 //
 //                        The Subzero Code Generator
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 ///
 /// \file
@@ skipping 219 matching lines @@
   void lowerInsertElement(const InstInsertElement *Inst) override;
   void lowerLoad(const InstLoad *Inst) override;
   void lowerPhi(const InstPhi *Inst) override;
   void lowerRet(const InstRet *Inst) override;
   void lowerSelect(const InstSelect *Inst) override;
   void lowerStore(const InstStore *Inst) override;
   void lowerSwitch(const InstSwitch *Inst) override;
   void lowerUnreachable(const InstUnreachable *Inst) override;
   void prelowerPhis() override;
   uint32_t getCallStackArgumentsSizeBytes(const InstCall *Instr) override;
-  void genTargetHelperCallFor(Inst *Instr) override { (void)Instr; }
+  void genTargetHelperCallFor(Inst *Instr) override;
   void doAddressOptLoad() override;
   void doAddressOptStore() override;
   void randomlyInsertNop(float Probability,
                          RandomNumberGenerator &RNG) override;
 
   OperandARM32Mem *formMemoryOperand(Operand *Ptr, Type Ty);
 
   Variable64On32 *makeI64RegPair();
   Variable *makeReg(Type Ty, int32_t RegNum = Variable::NoRegister);
   static Type stackSlotType();
@@ skipping 602 matching lines @@
   bool MaybeLeafFunc = true;
   size_t SpillAreaSizeBytes = 0;
   size_t FixedAllocaSizeBytes = 0;
   size_t FixedAllocaAlignBytes = 0;
   bool PrologEmitsFixedAllocas = false;
   uint32_t MaxOutArgsSizeBytes = 0;
   // TODO(jpp): std::array instead of array.
   static llvm::SmallBitVector TypeToRegisterSet[RCARM32_NUM];
   static llvm::SmallBitVector RegisterAliases[RegARM32::Reg_NUM];
   static llvm::SmallBitVector ScratchRegs;
+  /// Helper class that understands the Calling Convention and register
+  /// assignments. The first few integer type parameters can use r0-r3,

[Jim Stichnoth, 2015/11/24 22:24:00]

sentence ends in a comma - is there more that got stripped out?

[John, 2015/11/25 16:39:56]

No idea what happened here.

   llvm::SmallBitVector RegsUsed;
   VarList PhysicalRegisters[IceType_NUM];
 
   /// Helper class that understands the Calling Convention and register
   /// assignments. The first few integer type parameters can use r0-r3,
   /// regardless of their position relative to the floating-point/vector
   /// arguments in the argument list. Floating-point and vector arguments
   /// can use q0-q3 (aka d0-d7, s0-s15). For more information on the topic,
   /// see the ARM Architecture Procedure Calling Standards (AAPCS).
   ///
@@ skipping 37 matching lines @@
     llvm::SmallBitVector ValidF64Regs;
     llvm::SmallBitVector ValidV128Regs;
   };
 
 private:
   ~TargetARM32() override = default;
 
   OperandARM32Mem *formAddressingMode(Type Ty, Cfg *Func, const Inst *LdSt,
                                       Operand *Base);
 
+  void DoNothingHelper(const InstCall *) {}
+  void DivRem64Helper(const InstCall *Inst);
+  std::unordered_map<Operand *, void (TargetARM32::*)(const InstCall *Inst)>
+      ARM32Helpers;
+
   class BoolComputationTracker {
   public:
     BoolComputationTracker() = default;
     ~BoolComputationTracker() = default;
 
     void forgetProducers() { KnownComputations.clear(); }
     void recordProducers(CfgNode *Node);
 
     const Inst *getProducerOf(const Operand *Opnd) const {
       auto *Var = llvm::dyn_cast<Variable>(Opnd);
@@ skipping 108 matching lines @@
 
 private:
   ~TargetHeaderARM32() = default;
 
   TargetARM32Features CPUFeatures;
 };
 
 } // end of namespace Ice
 
 #endif // SUBZERO_SRC_ICETARGETLOWERINGARM32_H