Subzero. ARM32. Pre-lowers calls to ARM32 Helpers.

src/IceTargetLoweringARM32.cpp

 //===- subzero/src/IceTargetLoweringARM32.cpp - ARM32 lowering ------------===//
 //
 //                        The Subzero Code Generator
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 ///
 /// \file
@@ skipping 247 matching lines @@
       }
     }
 
     OutArgsSizeBytes = applyStackAlignmentTy(OutArgsSizeBytes, Ty);
     OutArgsSizeBytes += typeWidthInBytesOnStack(Ty);
   }
 
   return applyStackAlignment(OutArgsSizeBytes);
 }
 
+void TargetARM32::genTargetHelperCallFor(Inst *Instr) {
+  switch (Instr->getKind()) {
+  default:
+    return;
+  case Inst::Arithmetic: {
+    Variable *Dest = Instr->getDest();
+    const Type DestTy = Dest->getType();
+    if (DestTy == IceType_i64) {
+      const InstArithmetic::OpKind Op =
+          llvm::cast<InstArithmetic>(Instr)->getOp();
+      Operand *TargetHelper = nullptr;
+      switch (Op) {
+      default:
+        break;

[Jim Stichnoth, 2015/11/24 22:24:00]

maybe just return here?

[John, 2015/11/25 16:39:56]

Done.

+      case InstArithmetic::Udiv:
+        TargetHelper = Ctx->getConstantExternSym(H_udiv_i64);
+        break;
+      case InstArithmetic::Sdiv:
+        TargetHelper = Ctx->getConstantExternSym(H_sdiv_i64);
+        break;
+      case InstArithmetic::Urem:
+        TargetHelper = Ctx->getConstantExternSym(H_urem_i64);
+        break;
+      case InstArithmetic::Srem:
+        TargetHelper = Ctx->getConstantExternSym(H_srem_i64);
+        break;
+      }
+      if (TargetHelper == nullptr) {
+        return;
+      }
+      ARM32Helpers[TargetHelper] = &TargetARM32::DivRem64Helper;
+      constexpr SizeT MaxArgs = 2;
+      constexpr bool NoTailCall = false;
+      constexpr bool IsTargetHelperCall = true;
+      auto *Call = InstCall::create(Func, MaxArgs, Dest, TargetHelper,
+                                    NoTailCall, IsTargetHelperCall);
+      Call->addArg(Instr->getSrc(0));
+      Call->addArg(Instr->getSrc(1));
+      Context.insert(Call);
+      Instr->setDeleted();
+    }
+    return;
+  }
+  }
+}
+
 void TargetARM32::findMaxStackOutArgsSize() {
   // MinNeededOutArgsBytes should be updated if the Target ever creates a
   // high-level InstCall that requires more stack bytes.
   constexpr size_t MinNeededOutArgsBytes = 0;
   MaxOutArgsSizeBytes = MinNeededOutArgsBytes;
   for (CfgNode *Node : Func->getNodes()) {
     Context.init(Node);
     while (!Context.atEnd()) {
       PostIncrLoweringContext PostIncrement(Context);
       Inst *CurInstr = Context.getCur();
@@ skipping 1357 matching lines @@
   }
 
   Operand *invertedSrc1F(TargetARM32 *Target) const {
     return legalizeToRegOrFlex(Target,
                                Target->getCtx()->getConstantInt32(
                                    ~static_cast<uint32_t>(getConstantValue())));
   }
 };
 } // end of anonymous namespace
 
+void TargetARM32::DivRem64Helper(const InstCall *Instr) {
+  Operand *Src0 = Instr->getArg(0);
+  Operand *Src1 = Instr->getArg(1);
+  Int32Operands SrcsLo(loOperand(Src0), loOperand(Src1));
+  Int32Operands SrcsHi(hiOperand(Src0), hiOperand(Src1));
+  // Check for divide by 0 (ARM normally doesn't trap, but we want it to
+  // trap for NaCl). Src1Lo and Src1Hi may have already been legalized to a
+  // register, which will hide a constant source operand. Instead, check
+  // the not-yet-legalized Src1 to optimize-out a divide by 0 check.
+  if (!SrcsLo.swappedOperands() && SrcsLo.hasConstOperand()) {
+    if (SrcsLo.getConstantValue() == 0 && SrcsHi.getConstantValue() == 0) {
+      _trap();
+      return;
+    }
+  } else {
+    Operand *Src1Lo = SrcsLo.unswappedSrc1R(this);
+    Operand *Src1Hi = SrcsHi.unswappedSrc1R(this);
+    div0Check(IceType_i64, Src1Lo, Src1Hi);
+  }
+}
+
 void TargetARM32::lowerInt64Arithmetic(InstArithmetic::OpKind Op,
                                        Variable *Dest, Operand *Src0,
                                        Operand *Src1) {
   Int32Operands SrcsLo(loOperand(Src0), loOperand(Src1));
   Int32Operands SrcsHi(hiOperand(Src0), hiOperand(Src1));
   assert(SrcsLo.swappedOperands() == SrcsHi.swappedOperands());
   assert(SrcsLo.hasConstOperand() == SrcsHi.hasConstOperand());
 
   // These helper-call-involved instructions are lowered in this separate
   // switch. This is because we would otherwise assume that we need to
   // legalize Src0 to Src0RLo and Src0Hi. However, those go unused with
   // helper calls, and such unused/redundant instructions will fail liveness
   // analysis under -Om1 setting.
   switch (Op) {
   default:
     break;
   case InstArithmetic::Udiv:
   case InstArithmetic::Sdiv:
   case InstArithmetic::Urem:
   case InstArithmetic::Srem: {
-    // Check for divide by 0 (ARM normally doesn't trap, but we want it to
-    // trap for NaCl). Src1Lo and Src1Hi may have already been legalized to a
-    // register, which will hide a constant source operand. Instead, check
-    // the not-yet-legalized Src1 to optimize-out a divide by 0 check.
-    if (!SrcsLo.swappedOperands() && SrcsLo.hasConstOperand()) {
-      if (SrcsLo.getConstantValue() == 0 && SrcsHi.getConstantValue() == 0) {
-        _trap();
-        return;
-      }
-    } else {
-      Operand *Src1Lo = SrcsLo.unswappedSrc1R(this);
-      Operand *Src1Hi = SrcsHi.unswappedSrc1R(this);
-      div0Check(IceType_i64, Src1Lo, Src1Hi);
-    }
     // Technically, ARM has its own aeabi routines, but we can use the
     // non-aeabi routine as well. LLVM uses __aeabi_ldivmod for div, but uses
     // the more standard __moddi3 for rem.
     const char *HelperName = "";
     switch (Op) {
     default:
       llvm::report_fatal_error("Should have only matched div ops.");
       break;
     case InstArithmetic::Udiv:
       HelperName = H_udiv_i64;
@@ skipping 986 matching lines @@
   case CondARM32::kNone:
     _br(TargetFalse);
     break;
   case CondARM32::AL:
     _br(TargetTrue);
     break;
   }
 }
 
 void TargetARM32::lowerCall(const InstCall *Instr) {
+  Operand *CallTarget = Instr->getCallTarget();
+  if (Instr->isTargetHelperCall()) {
+    (this->*ARM32Helpers[CallTarget])(Instr);
+  }
   MaybeLeafFunc = false;
   NeedsStackAlignment = true;
 
   // Assign arguments to registers and stack. Also reserve stack.
   TargetARM32::CallingConv CC;
   // Pair of Arg Operand -> GPR number assignments.
   llvm::SmallVector<std::pair<Operand *, int32_t>,
                     TargetARM32::CallingConv::ARM32_MAX_GPR_ARG> GPRArgs;
   llvm::SmallVector<std::pair<Operand *, int32_t>,
                     TargetARM32::CallingConv::ARM32_MAX_FP_REG_UNITS> FPArgs;
@@ skipping 102 matching lines @@
     case IceType_v8i1:
     case IceType_v16i1:
     case IceType_v16i8:
     case IceType_v8i16:
     case IceType_v4i32:
     case IceType_v4f32:
       ReturnReg = makeReg(Dest->getType(), RegARM32::Reg_q0);
       break;
     }
   }
-  Operand *CallTarget = Instr->getCallTarget();
   // TODO(jvoung): Handle sandboxing. const bool NeedSandboxing =
   // Ctx->getFlags().getUseSandboxing();
 
   // Allow ConstantRelocatable to be left alone as a direct call, but force
   // other constants like ConstantInteger32 to be in a register and make it an
   // indirect call.
   if (!llvm::isa<ConstantRelocatable>(CallTarget)) {
     CallTarget = legalize(CallTarget, Legal_Reg);
   }
 
@@ skipping 2912 matching lines @@
   // Technically R9 is used for TLS with Sandboxing, and we reserve it.
   // However, for compatibility with current NaCl LLVM, don't claim that.
   Str << ".eabi_attribute 14, 3   @ Tag_ABI_PCS_R9_use: Not used\n";
 }
 
 llvm::SmallBitVector TargetARM32::TypeToRegisterSet[IceType_NUM];
 llvm::SmallBitVector TargetARM32::RegisterAliases[RegARM32::Reg_NUM];
 llvm::SmallBitVector TargetARM32::ScratchRegs;
 
 } // end of namespace Ice