Delete Assembler::FlushICacheWithoutIsolate

src/mips64/assembler-mips64.cc

 // Copyright (c) 1994-2006 Sun Microsystems Inc.
 // All Rights Reserved.
 //
 // Redistribution and use in source and binary forms, with or without
 // modification, are permitted provided that the following conditions are
 // met:
 //
 // - Redistributions of source code must retain the above copyright notice,
 // this list of conditions and the following disclaimer.
 //
@@ skipping 3222 matching lines @@
 //    1: ori(rd, rd, (j.imm64_ >> 16) & kImm16Mask);
 //    2: dsll(rd, rd, 16);
 //    3: ori(rd, rd, j.imm32_ & kImm16Mask);
 //
 // Patching the address must replace all the lui & ori instructions,
 // and flush the i-cache.
 //
 // There is an optimization below, which emits a nop when the address
 // fits in just 16 bits. This is unlikely to help, and should be benchmarked,
 // and possibly removed.
-void Assembler::set_target_address_at(Address pc,
+void Assembler::set_target_address_at(Isolate* isolate, Address pc,
                                       Address target,
                                       ICacheFlushMode icache_flush_mode) {
 // There is an optimization where only 4 instructions are used to load address
 // in code on MIP64 because only 48-bits of address is effectively used.
 // It relies on fact the upper [63:48] bits are not used for virtual address
 // translation and they have to be set according to value of bit 47 in order
 // get canonical address.
   Instr instr1 = instr_at(pc + kInstrSize);
   uint32_t rt_code = GetRt(instr1);
   uint32_t* p = reinterpret_cast<uint32_t*>(pc);
@@ skipping 12 matching lines @@
   // ori rt, rt, lower-16.
   // dsll rt, rt, 16.
   // ori rt rt, lower-16.
   *p = LUI | (rt_code << kRtShift) | ((itarget >> 32) & kImm16Mask);
   *(p + 1) = ORI | (rt_code << kRtShift) | (rt_code << kRsShift)
       | ((itarget >> 16) & kImm16Mask);
   *(p + 3) = ORI | (rt_code << kRsShift) | (rt_code << kRtShift)
       | (itarget & kImm16Mask);
 
   if (icache_flush_mode != SKIP_ICACHE_FLUSH) {
-    Assembler::FlushICacheWithoutIsolate(pc, 4 * Assembler::kInstrSize);
+    Assembler::FlushICache(isolate, pc, 4 * Assembler::kInstrSize);
   }
 }
 
 
 }  // namespace internal
 }  // namespace v8
 
 #endif  // V8_TARGET_ARCH_MIPS64