Delete Assembler::FlushICacheWithoutIsolate

src/full-codegen/mips64/full-codegen-mips64.cc

 // Copyright 2012 the V8 project authors. All rights reserved.
 // Use of this source code is governed by a BSD-style license that can be
 // found in the LICENSE file.
 
 #if V8_TARGET_ARCH_MIPS64
 
 // Note on Mips implementation:
 //
 // The result_register() for mips is the 'v0' register, which is defined
 // by the ABI to contain function return values. However, the first
@@ skipping 4927 matching lines @@
       // ori  t9, <on-stack replacement address> lower
       // jalr t9  ;; Not changed
       // nop  ;; Not changed
       // ok-label ----- pc_after points here
       patcher.masm()->daddiu(at, zero_reg, 1);
       break;
   }
   Address pc_immediate_load_address = pc - 6 * kInstrSize;
   // Replace the stack check address in the load-immediate (6-instr sequence)
   // with the entry address of the replacement code.
-  Assembler::set_target_address_at(pc_immediate_load_address,
+  Assembler::set_target_address_at(unoptimized_code->GetIsolate(),
+                                   pc_immediate_load_address,
                                    replacement_code->entry());
 
   unoptimized_code->GetHeap()->incremental_marking()->RecordCodeTargetPatch(
       unoptimized_code, pc_immediate_load_address, replacement_code);
 }
 
 
 BackEdgeTable::BackEdgeState BackEdgeTable::GetBackEdgeState(
     Isolate* isolate,
     Code* unoptimized_code,
@@ skipping 25 matching lines @@
          reinterpret_cast<uint64_t>(
              isolate->builtins()->OsrAfterStackCheck()->entry()));
   return OSR_AFTER_STACK_CHECK;
 }
 
 
 }  // namespace internal
 }  // namespace v8
 
 #endif  // V8_TARGET_ARCH_MIPS64