On MIPS, uses more branch delay slots.

runtime/vm/flow_graph_compiler_mips.cc

 // Copyright (c) 2013, the Dart project authors.  Please see the AUTHORS file
 // for details. All rights reserved. Use of this source code is governed by a
 // BSD-style license that can be found in the LICENSE file.
 
 #include "vm/globals.h"  // Needed here to get TARGET_ARCH_MIPS.
 #if defined(TARGET_ARCH_MIPS)
 
 #include "vm/flow_graph_compiler.h"
 
 #include "lib/error.h"
@@ skipping 73 matching lines @@
     Register type_arguments_reg,
     Register temp_reg,
     Label* is_instance_lbl,
     Label* is_not_instance_lbl) {
   __ TraceSimMsg("CallSubtypeTestStub");
   ASSERT(instance_reg == A0);
   ASSERT(temp_reg == kNoRegister);  // Unused on MIPS.
   const SubtypeTestCache& type_test_cache =
       SubtypeTestCache::ZoneHandle(SubtypeTestCache::New());
   __ LoadObject(A2, type_test_cache);
+  intptr_t null = reinterpret_cast<intptr_t>(Object::null());
+  uint16_t null_lo = Utils::Low16Bits(null);
+  uint16_t null_hi = Utils::High16Bits(null);
   if (test_kind == kTestTypeOneArg) {
     ASSERT(type_arguments_reg == kNoRegister);
-    __ LoadImmediate(A1, reinterpret_cast<intptr_t>(Object::null()));
+    __ lui(A1, Immediate(null_hi));
     __ BranchLink(&StubCode::Subtype1TestCacheLabel());
+    __ delay_slot()->ori(A1, A1, Immediate(null_lo));
   } else if (test_kind == kTestTypeTwoArgs) {
     ASSERT(type_arguments_reg == kNoRegister);
-    __ LoadImmediate(A1, reinterpret_cast<intptr_t>(Object::null()));
+    __ lui(A1, Immediate(null_hi));
     __ BranchLink(&StubCode::Subtype2TestCacheLabel());
+    __ delay_slot()->ori(A1, A1, Immediate(null_lo));
   } else if (test_kind == kTestTypeThreeArgs) {
     ASSERT(type_arguments_reg == A1);
     __ BranchLink(&StubCode::Subtype3TestCacheLabel());
   } else {
     UNREACHABLE();
   }
   // Result is in V0: null -> not found, otherwise Bool::True or Bool::False.
   GenerateBoolToJump(V0, is_instance_lbl, is_not_instance_lbl);
   return type_test_cache.raw();
 }
@@ skipping 350 matching lines @@
   __ TraceSimMsg("AssertAssignable");
   ASSERT(token_pos >= 0);
   ASSERT(!dst_type.IsNull());
   ASSERT(dst_type.IsFinalized());
   // Assignable check is skipped in FlowGraphBuilder, not here.
   ASSERT(dst_type.IsMalformed() ||
          (!dst_type.IsDynamicType() && !dst_type.IsObjectType()));
   // Preserve instantiator and its type arguments.
   __ addiu(SP, SP, Immediate(-2 * kWordSize));
   __ sw(A2, Address(SP, 1 * kWordSize));
-  __ sw(A1, Address(SP, 0 * kWordSize));
+
   // A null object is always assignable and is returned as result.
   Label is_assignable, runtime_call;
   __ BranchEqual(A0, reinterpret_cast<int32_t>(Object::null()), &is_assignable);
+  __ delay_slot()->sw(A1, Address(SP, 0 * kWordSize));
 
   if (!FLAG_eliminate_type_checks) {
     // If type checks are not eliminated during the graph building then
     // a transition sentinel can be seen here.
     __ BranchEqual(A0, Object::transition_sentinel(), &is_assignable);
   }
 
   // Generate throw new TypeError() if the type is malformed.
   if (dst_type.IsMalformed()) {
     const Error& error = Error::Handle(dst_type.malformed_error());
@@ skipping 133 matching lines @@
   __ subu(T1, T1, T2);
   __ sll(T1, T1, 1);
   __ addu(T1, FP, T1);
   __ AddImmediate(T1, kLastParamSlotIndex * kWordSize);
 
   // Let T0 point to the last copied positional argument, i.e. to
   // fp[kFirstLocalSlotIndex - (num_pos_args - 1)].
   __ AddImmediate(T0, FP, (kFirstLocalSlotIndex + 1) * kWordSize);
   __ sll(T2, T2, 1);  // T2 is a Smi.
 
-  Label loop, loop_condition;
-  __ b(&loop_condition);
+  Label loop, loop_exit;
+  __ blez(T2, &loop_exit);
   __ delay_slot()->subu(T0, T0, T2);
-  // We do not use the final allocation index of the variable here, i.e.
-  // scope->VariableAt(i)->index(), because captured variables still need
-  // to be copied to the context that is not yet allocated.
   __ Bind(&loop);
   __ addu(T4, T1, T2);
+  __ lw(T3, Address(T4, -kWordSize));
+  __ addiu(T2, T2, Immediate(-kWordSize));
   __ addu(T5, T0, T2);
-  __ lw(T3, Address(T4));
-  __ sw(T3, Address(T5));
-  __ Bind(&loop_condition);
-  __ addiu(T2, T2, Immediate(-kWordSize));
-  __ bgez(T2, &loop);
+  __ bgtz(T2, &loop);
+  __ delay_slot()->sw(T3, Address(T5));
+  __ Bind(&loop_exit);
 
   // Copy or initialize optional named arguments.
   Label all_arguments_processed;
   if (num_opt_named_params > 0) {
     // Start by alphabetically sorting the names of the optional parameters.
     LocalVariable** opt_param = new LocalVariable*[num_opt_named_params];
     int* opt_param_position = new int[num_opt_named_params];
     for (int pos = num_fixed_params; pos < num_params; pos++) {
       LocalVariable* parameter = scope->VariableAt(pos);
       const String& opt_param_name = parameter->name();
@@ skipping 132 matching lines @@
   __ LeaveDartFrame();
   __ Ret();
 
   __ Bind(&all_arguments_processed);
   // Nullify originally passed arguments only after they have been copied and
   // checked, otherwise noSuchMethod would not see their original values.
   // This step can be skipped in case we decide that formal parameters are
   // implicitly final, since garbage collecting the unmodified value is not
   // an issue anymore.
 
+  __ LoadImmediate(T0, reinterpret_cast<intptr_t>(Object::null()));
+
   // S4 : arguments descriptor array.
   __ lw(T2, FieldAddress(S4, ArgumentsDescriptor::count_offset()));
   __ sll(T2, T2, 1);  // T2 is a Smi.
 
-  __ LoadImmediate(T0, reinterpret_cast<intptr_t>(Object::null()));
-  Label null_args_loop, null_args_loop_condition;
-
-  __ b(&null_args_loop_condition);
+  Label null_args_loop, null_args_loop_exit;
+  __ blez(T2, &null_args_loop_exit);
   __ delay_slot()->addiu(T1, FP, Immediate(kLastParamSlotIndex * kWordSize));
-
   __ Bind(&null_args_loop);
+  __ addiu(T2, T2, Immediate(-kWordSize));
   __ addu(T3, T1, T2);
-  __ sw(T0, Address(T3));
-
-  __ Bind(&null_args_loop_condition);
-  __ addiu(T2, T2, Immediate(-kWordSize));
-  __ bgez(T2, &null_args_loop);
+  __ bgtz(T2, &null_args_loop);
+  __ delay_slot()->sw(T0, Address(T3));
+  __ Bind(&null_args_loop_exit);
 }
 
 
 void FlowGraphCompiler::GenerateInlinedGetter(intptr_t offset) {
   // RA: return address.
   // SP: receiver.
   // Sequence node has one return node, its input is load field node.
   __ lw(V0, Address(SP, 0 * kWordSize));
   __ lw(V0, Address(V0, offset - kHeapObjectTag));
   __ Ret();
 }
 
 
 void FlowGraphCompiler::GenerateInlinedSetter(intptr_t offset) {
   // RA: return address.
   // SP+1: receiver.
   // SP+0: value.
   // Sequence node has one store node and one return NULL node.
   __ lw(T0, Address(SP, 1 * kWordSize));  // Receiver.
   __ lw(T1, Address(SP, 0 * kWordSize));  // Value.
   __ StoreIntoObject(T0, FieldAddress(T0, offset), T1);
-  __ LoadImmediate(V0, reinterpret_cast<intptr_t>(Object::null()));
+  intptr_t null = reinterpret_cast<intptr_t>(Object::null());
+  uint16_t null_lo = Utils::Low16Bits(null);
+  uint16_t null_hi = Utils::High16Bits(null);
+  __ lui(V0, Immediate(null_hi));
   __ Ret();
+  __ delay_slot()->ori(V0, V0, Immediate(null_lo));
 }
 
 
 void FlowGraphCompiler::EmitFrameEntry() {
   __ TraceSimMsg("FrameEntry");
   const Function& function = parsed_function().function();
   if (CanOptimizeFunction() && function.is_optimizable()) {
     const bool can_optimize = !is_optimizing() || may_reoptimize();
     const Register function_reg = T0;
     if (can_optimize) {
@@ skipping 353 matching lines @@
 
 
 void FlowGraphCompiler::EmitEqualityRegConstCompare(Register reg,
                                                     const Object& obj,
                                                     bool needs_number_check) {
   if (needs_number_check &&
       (obj.IsMint() || obj.IsDouble() || obj.IsBigint())) {
     __ addiu(SP, SP, Immediate(-2 * kWordSize));
     __ sw(reg, Address(SP, 1 * kWordSize));
     __ LoadObject(TMP1, obj);
-    __ sw(TMP1, Address(SP, 0 * kWordSize));
     __ BranchLink(&StubCode::IdenticalWithNumberCheckLabel());
+    __ delay_slot()->sw(TMP1, Address(SP, 0 * kWordSize));
     __ lw(reg, Address(SP, 1 * kWordSize));  // Restore 'reg'.
     __ addiu(SP, SP, Immediate(2 * kWordSize));  // Discard constant.
     return;
   }
   __ CompareObject(CMPRES, reg, obj);
 }
 
 
 void FlowGraphCompiler::EmitEqualityRegRegCompare(Register left,
                                                   Register right,
                                                   bool needs_number_check) {
   __ TraceSimMsg("EqualityRegRegCompare");
   if (needs_number_check) {
     __ addiu(SP, SP, Immediate(-2 * kWordSize));
     __ sw(left, Address(SP, 1 * kWordSize));
-    __ sw(right, Address(SP, 0 * kWordSize));
     __ BranchLink(&StubCode::IdenticalWithNumberCheckLabel());
+    __ delay_slot()->sw(right, Address(SP, 0 * kWordSize));
     __ TraceSimMsg("EqualityRegRegCompare return");
     // Stub returns result in CMPRES. If it is 0, then left and right are equal.
     __ lw(right, Address(SP, 0 * kWordSize));
     __ lw(left, Address(SP, 1 * kWordSize));
     __ addiu(SP, SP, Immediate(2 * kWordSize));
   } else {
     __ subu(CMPRES, left, right);
   }
 }
 
@@ skipping 328 matching lines @@
   __ AddImmediate(SP, kDoubleSize);
 }
 
 
 #undef __
 
 
 }  // namespace dart
 
 #endif  // defined TARGET_ARCH_MIPS