[turbofan] Simplified splintering code.

src/compiler/pipeline.cc

 // Copyright 2014 the V8 project authors. All rights reserved.
 // Use of this source code is governed by a BSD-style license that can be
 // found in the LICENSE file.
 
 #include "src/compiler/pipeline.h"
 
 #include <fstream>  // NOLINT(readability/streams)
 #include <sstream>
 
 #include "src/base/adapters.h"
@@ skipping 826 matching lines @@
   static const char* phase_name() { return "allocate double registers"; }
 
   void Run(PipelineData* data, Zone* temp_zone) {
     RegAllocator allocator(data->register_allocation_data(), DOUBLE_REGISTERS,
                            temp_zone);
     allocator.AllocateRegisters();
   }
 };
 
 
+struct MarkSpilledOnlyInDeferredPhase {

[Jarin, 2015/11/25 10:33:08]

I think there is no need to introduce a new phase for this. It could be done as
part of MergeSplintersPhase.

[Mircea Trofin, 2015/11/25 16:21:36]

It can be done, but it seemed cleaner to have it separate - merged it in for
now, because I can't find a better defense for separation than "it seems
cleaner".

+  static const char* phase_name() {
+    return "mark ranges spilled in deferred blocks";
+  }
+
+  void Run(PipelineData* pipeline_data, Zone* temp_zone) {
+    RegisterAllocationData* data = pipeline_data->register_allocation_data();
+    for (TopLevelLiveRange* top : data->live_ranges()) {

[Jarin, 2015/11/25 10:33:08]

The pipeline should not know about implementation details, such as the live
range data structure. The code here should be moved to a method of the register
allocator and the method should be called from here.

[Mircea Trofin, 2015/11/25 16:21:36]

done as a side-effect of addressing the above.

+      if (top == nullptr || top->IsEmpty() || top->splinter() == nullptr) {
+        continue;
+      }
+
+      LiveRange* child = top;
+      for (; child != nullptr; child = child->next()) {
+        if (child->spilled() ||
+            child->NextSlotPosition(child->Start()) != nullptr) {
+          break;
+        }
+      }
+      if (child == nullptr) top->MarkSpilledInDeferredBlock();
+    }
+  }
+};
+
+
 struct MergeSplintersPhase {
   static const char* phase_name() { return "merge splintered ranges"; }
   void Run(PipelineData* pipeline_data, Zone* temp_zone) {
     RegisterAllocationData* data = pipeline_data->register_allocation_data();
     LiveRangeMerger live_range_merger(data, temp_zone);
     live_range_merger.Merge();
   }
 };
 
 
@@ skipping 512 matching lines @@
   Run<ResolvePhisPhase>();
   Run<BuildLiveRangesPhase>();
   if (FLAG_trace_turbo_graph) {
     OFStream os(stdout);
     PrintableInstructionSequence printable = {config, data->sequence()};
     os << "----- Instruction sequence before register allocation -----\n"
        << printable;
   }
   if (verifier != nullptr) {
     CHECK(!data->register_allocation_data()->ExistsUseWithoutDefinition());
+    CHECK(data->register_allocation_data()
+              ->RangesDefinedInDeferredStaysInDeferred());
   }
 
   if (FLAG_turbo_preprocess_ranges) {
     Run<SplinterLiveRangesPhase>();
   }
 
   if (FLAG_turbo_greedy_regalloc) {
     Run<AllocateGeneralRegistersPhase<GreedyAllocator>>();
     Run<AllocateDoubleRegistersPhase<GreedyAllocator>>();
   } else {
     Run<AllocateGeneralRegistersPhase<LinearScanAllocator>>();
     Run<AllocateDoubleRegistersPhase<LinearScanAllocator>>();
   }
 
   if (FLAG_turbo_preprocess_ranges) {
+    Run<MarkSpilledOnlyInDeferredPhase>();
     Run<MergeSplintersPhase>();
   }
 
   if (FLAG_turbo_frame_elision) {
     Run<LocateSpillSlotsPhase>();
     Run<FrameElisionPhase>();
   }
 
   Run<AssignSpillSlotsPhase>();
 
@@ skipping 22 matching lines @@
     tcf << AsC1VRegisterAllocationData("CodeGen",
                                        data->register_allocation_data());
   }
 
   data->DeleteRegisterAllocationZone();
 }
 
 }  // namespace compiler
 }  // namespace internal
 }  // namespace v8