Unify alloca, outgoing arg, and prolog construction

src/IceTargetLoweringX86Base.h

 //===- subzero/src/IceTargetLoweringX86Base.h - x86 lowering ----*- C++ -*-===//
 //
 //                        The Subzero Code Generator
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 ///
 /// \file
@@ skipping 91 matching lines @@
     return Traits::X86_STACK_ALIGNMENT_BYTES;
   }
   void reserveFixedAllocaArea(size_t Size, size_t Align) override {
     FixedAllocaSizeBytes = Size;
     assert(llvm::isPowerOf2_32(Align));
     FixedAllocaAlignBytes = Align;
     PrologEmitsFixedAllocas = true;
   }
   /// Returns the (negative) offset from ebp/rbp where the fixed Allocas start.
   int32_t getFrameFixedAllocaOffset() const override {
-    return FixedAllocaSizeBytes - SpillAreaSizeBytes;
+    return FixedAllocaSizeBytes - (SpillAreaSizeBytes - maxOutArgsSizeBytes());
+  }
+  virtual uint32_t maxOutArgsSizeBytes() const override {
+    return MaxOutArgsSizeBytes;
+  }
+  virtual void updateMaxOutArgsSizeBytes(uint32_t Size) {
+    MaxOutArgsSizeBytes = std::max(MaxOutArgsSizeBytes, Size);
   }
 
   bool shouldSplitToVariable64On32(Type Ty) const override {
     return Traits::Is64Bit ? false : Ty == IceType_i64;
   }
 
   SizeT getMinJumpTableSize() const override { return 4; }
 
   void emitVariable(const Variable *Var) const override;
 
@@ skipping 52 matching lines @@
   void lowerInsertElement(const InstInsertElement *Inst) override;
   void lowerLoad(const InstLoad *Inst) override;
   void lowerPhi(const InstPhi *Inst) override;
   void lowerSelect(const InstSelect *Inst) override;
   void lowerStore(const InstStore *Inst) override;
   void lowerSwitch(const InstSwitch *Inst) override;
   void lowerUnreachable(const InstUnreachable *Inst) override;
   void lowerOther(const Inst *Instr) override;
   void lowerRMW(const typename Traits::Insts::FakeRMW *RMW);
   void prelowerPhis() override;
+  uint32_t getCallStackArgumentsSizeBytes(const std::vector<Type> &ArgTypes,
+                                          Type ReturnType);
   uint32_t getCallStackArgumentsSizeBytes(const InstCall *Instr) override;
-  void genTargetHelperCallFor(Inst *Instr) override { (void)Instr; }
+  void genTargetHelperCallFor(Inst *Instr) override;
   void doAddressOptLoad() override;
   void doAddressOptStore() override;
   void doMockBoundsCheck(Operand *Opnd) override;
   void randomlyInsertNop(float Probability,
                          RandomNumberGenerator &RNG) override;
 
   /// Naive lowering of cmpxchg.
   void lowerAtomicCmpxchg(Variable *DestPrev, Operand *Ptr, Operand *Expected,
                           Operand *Desired);
   /// Attempt a more optimized lowering of cmpxchg. Returns true if optimized.
@@ skipping 126 matching lines @@
   }
   void _adc_rmw(typename Traits::X86OperandMem *DestSrc0, Operand *Src1) {
     Context.insert(Traits::Insts::AdcRMW::create(Func, DestSrc0, Src1));
   }
   void _add(Variable *Dest, Operand *Src0) {
     Context.insert(Traits::Insts::Add::create(Func, Dest, Src0));
   }
   void _add_rmw(typename Traits::X86OperandMem *DestSrc0, Operand *Src1) {
     Context.insert(Traits::Insts::AddRMW::create(Func, DestSrc0, Src1));
   }
-  void _adjust_stack(int32_t Amount) {
-    Context.insert(Traits::Insts::AdjustStack::create(
-        Func, Amount, getPhysicalRegister(Traits::RegisterSet::Reg_esp)));
-  }
   void _addps(Variable *Dest, Operand *Src0) {
     Context.insert(Traits::Insts::Addps::create(Func, Dest, Src0));
   }
   void _addss(Variable *Dest, Operand *Src0) {
     Context.insert(Traits::Insts::Addss::create(Func, Dest, Src0));
   }
   void _and(Variable *Dest, Operand *Src0) {
     Context.insert(Traits::Insts::And::create(Func, Dest, Src0));
   }
   void _and_rmw(typename Traits::X86OperandMem *DestSrc0, Operand *Src1) {
@@ skipping 351 matching lines @@
   void findRMW();
 
   typename Traits::InstructionSet InstructionSet =
       Traits::InstructionSet::Begin;
   bool IsEbpBasedFrame = false;
   bool NeedsStackAlignment = false;
   size_t SpillAreaSizeBytes = 0;
   size_t FixedAllocaSizeBytes = 0;
   size_t FixedAllocaAlignBytes = 0;
   bool PrologEmitsFixedAllocas = false;
+  uint32_t MaxOutArgsSizeBytes = 0;
   static std::array<llvm::SmallBitVector, RCX86_NUM> TypeToRegisterSet;
   static std::array<llvm::SmallBitVector, Traits::RegisterSet::Reg_NUM>
       RegisterAliases;
   static llvm::SmallBitVector ScratchRegs;
   llvm::SmallBitVector RegsUsed;
   std::array<VarList, IceType_NUM> PhysicalRegisters;
 
   /// Randomize a given immediate operand
   Operand *randomizeOrPoolImmediate(Constant *Immediate,
                                     int32_t RegNum = Variable::NoRegister);
@@ skipping 55 matching lines @@
   lowerIcmp64(const InstIcmp *Icmp, const InstBr *Br);
 
   BoolFolding FoldingInfo;
 };
 } // end of namespace X86Internal
 } // end of namespace Ice
 
 #include "IceTargetLoweringX86BaseImpl.h"
 
 #endif // SUBZERO_SRC_ICETARGETLOWERINGX86BASE_H