Unify alloca, outgoing arg, and prolog construction

tests_lit/llvm2ice_tests/alloc.ll

 ; This is a basic test of the alloca instruction.
 
 ; RUN: %if --need=target_X8632 --command %p2i --filetype=obj --disassemble \
 ; RUN:   --target x8632 -i %s --args -O2 -allow-externally-defined-symbols \
 ; RUN:   | %if --need=target_X8632 --command FileCheck %s
 
 ; RUN: %if --need=target_X8632 --command %p2i --filetype=obj --disassemble \
 ; RUN:   --target x8632 -i %s --args -Om1 -allow-externally-defined-symbols \
 ; RUN:   | %if --need=target_X8632 --command FileCheck \
 ; RUN:   --check-prefix CHECK-OPTM1 %s
@@ skipping 16 matching lines @@
 ; RUN:   --command FileCheck --check-prefix ARM32 --check-prefix=ARM-OPTM1 %s
 
 define internal void @fixed_416_align_16(i32 %n) {
 entry:
   %array = alloca i8, i32 416, align 16
   %__2 = ptrtoint i8* %array to i32
   call void @f1(i32 %__2)
   ret void
 }
 ; CHECK-LABEL: fixed_416_align_16
-; CHECK:      sub     esp,0x1ac
-; CHECK:      sub     esp,0x10
+; CHECK:      sub     esp,0x1bc
+; CHECK:      lea     eax,[esp+0x10]
 ; CHECK:      mov     DWORD PTR [esp],eax
 ; CHECK:      call {{.*}} R_{{.*}}    f1
 
 ; CHECK-OPTM1-LABEL: fixed_416_align_16
-; CHECK-OPTM1:      sub     esp,0xc
+; CHECK-OPTM1:      sub     esp,0x18
 ; CHECK-OPTM1:      sub     esp,0x1a0
-; CHECK-OPTM1:      sub     esp,0x10
 ; CHECK-OPTM1:      mov     DWORD PTR [esp],eax
 ; CHECK-OPTM1:      call {{.*}} R_{{.*}}    f1
 
 ; ARM32-LABEL: fixed_416_align_16
 ; ARM32-OPT2:  sub sp, sp, #428
 ; ARM32-OPTM1: sub sp, sp, #416
 ; ARM32:       bl {{.*}} R_{{.*}}    f1
 
 define internal void @fixed_416_align_32(i32 %n) {
 entry:
   %array = alloca i8, i32 400, align 32
   %__2 = ptrtoint i8* %array to i32
   call void @f1(i32 %__2)
   ret void
 }
 ; CHECK-LABEL: fixed_416_align_32
 ; CHECK:      push    ebp
 ; CHECK-NEXT: mov     ebp,esp
-; CHECK:      sub     esp,0x1a8
+; CHECK:      sub     esp,0x1b8
 ; CHECK:      and     esp,0xffffffe0
-; CHECK:      sub     esp,0x10
+; CHECK:      lea     eax,[esp+0x10]
 ; CHECK:      mov     DWORD PTR [esp],eax
 ; CHECK:      call {{.*}} R_{{.*}}    f1
 
 ; ARM32-LABEL: fixed_416_align_32
 ; ARM32-OPT2:  sub sp, sp, #424
 ; ARM32-OPTM1: sub sp, sp, #416
 ; ARM32:       bic sp, sp, #31
 ; ARM32:       bl {{.*}} R_{{.*}}    f1
 
 ; Show that the amount to allocate will be rounded up.
 define internal void @fixed_351_align_16(i32 %n) {
 entry:
   %array = alloca i8, i32 351, align 16
   %__2 = ptrtoint i8* %array to i32
   call void @f1(i32 %__2)
   ret void
 }
 ; CHECK-LABEL: fixed_351_align_16
-; CHECK:      sub     esp,0x16c
+; CHECK:      sub     esp,0x17c
+; CHECK:      lea     eax,[esp+0x10]
 ; CHECK:      mov     DWORD PTR [esp],eax
 ; CHECK:      call {{.*}} R_{{.*}}    f1
 
 ; CHECK-OPTM1-LABEL: fixed_351_align_16
-; CHECK-OPTM1:      sub     esp,0xc
+; CHECK-OPTM1:      sub     esp,0x18
 ; CHECK-OPTM1:      sub     esp,0x160
 ; CHECK-OPTM1:      mov     DWORD PTR [esp],eax
 ; CHECK-OPTM1:      call {{.*}} R_{{.*}}    f1
 
 ; ARM32-LABEL: fixed_351_align_16
 ; ARM32-OPT2:  sub sp, sp, #364
 ; ARM32-OPTM1: sub sp, sp, #352
 ; ARM32:       bl {{.*}} R_{{.*}}    f1
 
 define internal void @fixed_351_align_32(i32 %n) {
 entry:
   %array = alloca i8, i32 351, align 32
   %__2 = ptrtoint i8* %array to i32
   call void @f1(i32 %__2)
   ret void
 }
 ; CHECK-LABEL: fixed_351_align_32
 ; CHECK:      push    ebp
 ; CHECK-NEXT: mov     ebp,esp
-; CHECK:      sub     esp,0x168
+; CHECK:      sub     esp,0x178
 ; CHECK:      and     esp,0xffffffe0
-; CHECK:      sub     esp,0x10
+; CHECK:      lea     eax,[esp+0x10]
 ; CHECK:      mov     DWORD PTR [esp],eax
 ; CHECK:      call {{.*}} R_{{.*}}    f1
 
 ; ARM32-LABEL: fixed_351_align_32
 ; ARM32-OPT2:  sub sp, sp, #360
 ; ARM32-OPTM1: sub sp, sp, #352
 ; ARM32:       bic sp, sp, #31
 ; ARM32:       bl {{.*}} R_{{.*}}    f1
 
 declare void @f1(i32 %ignored)
 
 declare void @f2(i32 %ignored)
 
 define internal void @variable_n_align_16(i32 %n) {
 entry:
   %array = alloca i8, i32 %n, align 16
   %__2 = ptrtoint i8* %array to i32
   call void @f2(i32 %__2)
   ret void
 }
 ; CHECK-LABEL: variable_n_align_16
+; CHECK:      sub     esp,0x18
 ; CHECK:      mov     eax,DWORD PTR [ebp+0x8]
 ; CHECK:      add     eax,0xf
 ; CHECK:      and     eax,0xfffffff0
 ; CHECK:      sub     esp,eax
-; CHECK:      sub     esp,0x10
+; CHECK:      lea     eax,[esp+0x10]
 ; CHECK:      mov     DWORD PTR [esp],eax
 ; CHECK:      call {{.*}} R_{{.*}}    f2
 
 ; ARM32-LABEL: variable_n_align_16
 ; ARM32:      add r0, r0, #15
 ; ARM32:      bic r0, r0, #15
 ; ARM32:      sub sp, sp, r0
 ; ARM32:      bl {{.*}} R_{{.*}}    f2
 
 define internal void @variable_n_align_32(i32 %n) {
 entry:
   %array = alloca i8, i32 %n, align 32
   %__2 = ptrtoint i8* %array to i32
   call void @f2(i32 %__2)
   ret void
 }
 ; In -O2, the order of the CHECK-DAG lines in the output is switched.
 ; CHECK-LABEL: variable_n_align_32
 ; CHECK:      push    ebp
 ; CHECK:      mov     ebp,esp
+; CHECK:      sub     esp,0x18
 ; CHECK-DAG:  and     esp,0xffffffe0
 ; CHECK-DAG:  mov     eax,DWORD PTR [ebp+0x8]
 ; CHECK:      add     eax,0x1f
 ; CHECK:      and     eax,0xffffffe0
 ; CHECK:      sub     esp,eax
-; CHECK:      sub     esp,0x10
+; CHECK:      lea     eax,[esp+0x10]
 ; CHECK:      mov     DWORD PTR [esp],eax
 ; CHECK:      call {{.*}} R_{{.*}}    f2
 ; CHECK:      mov     esp,ebp
 ; CHECK:      pop     ebp
 
 ; ARM32-LABEL: variable_n_align_32
 ; ARM32:      push {fp, lr}
 ; ARM32:      mov fp, sp
 ; ARM32:      bic sp, sp, #31
 ; ARM32:      add r0, r0, #31
@@ skipping 118 matching lines @@
   %p1 = bitcast i8* %a1 to i32*
   %p2 = bitcast i8* %a2 to i32*
   %p3 = bitcast i8* %a3 to i32*
   store i32 %arg, i32* %p1, align 1
   store i32 %arg, i32* %p2, align 1
   store i32 %arg, i32* %p3, align 1
   ret void
 }
 ; CHECK-LABEL: var_with_frameptr
 ; CHECK:      mov     ebp,esp