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| 1 //===- subzero/src/IceTargetLoweringARM32.cpp - ARM32 lowering ------------===// | 1 //===- subzero/src/IceTargetLoweringARM32.cpp - ARM32 lowering ------------===// |
| 2 // | 2 // |
| 3 // The Subzero Code Generator | 3 // The Subzero Code Generator |
| 4 // | 4 // |
| 5 // This file is distributed under the University of Illinois Open Source | 5 // This file is distributed under the University of Illinois Open Source |
| 6 // License. See LICENSE.TXT for details. | 6 // License. See LICENSE.TXT for details. |
| 7 // | 7 // |
| 8 //===----------------------------------------------------------------------===// | 8 //===----------------------------------------------------------------------===// |
| 9 /// | 9 /// |
| 10 /// \file | 10 /// \file |
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| 842 uint32_t SpillAreaPaddingBytes = 0; | 842 uint32_t SpillAreaPaddingBytes = 0; |
| 843 uint32_t LocalsSlotsPaddingBytes = 0; | 843 uint32_t LocalsSlotsPaddingBytes = 0; |
| 844 alignStackSpillAreas(PreservedRegsSizeBytes, SpillAreaAlignmentBytes, | 844 alignStackSpillAreas(PreservedRegsSizeBytes, SpillAreaAlignmentBytes, |
| 845 GlobalsSize, LocalsSlotsAlignmentBytes, | 845 GlobalsSize, LocalsSlotsAlignmentBytes, |
| 846 &SpillAreaPaddingBytes, &LocalsSlotsPaddingBytes); | 846 &SpillAreaPaddingBytes, &LocalsSlotsPaddingBytes); |
| 847 SpillAreaSizeBytes += SpillAreaPaddingBytes + LocalsSlotsPaddingBytes; | 847 SpillAreaSizeBytes += SpillAreaPaddingBytes + LocalsSlotsPaddingBytes; |
| 848 uint32_t GlobalsAndSubsequentPaddingSize = | 848 uint32_t GlobalsAndSubsequentPaddingSize = |
| 849 GlobalsSize + LocalsSlotsPaddingBytes; | 849 GlobalsSize + LocalsSlotsPaddingBytes; |
| 850 | 850 |
| 851 // Adds the out args space to the stack, and align SP if necessary. | 851 // Adds the out args space to the stack, and align SP if necessary. |
| 852 if (!NeedsStackAlignment) { | 852 if (NeedsStackAlignment) { |
| 853 SpillAreaSizeBytes += MaxOutArgsSizeBytes; | |
| 854 } else { | |
| 855 uint32_t StackOffset = PreservedRegsSizeBytes; | 853 uint32_t StackOffset = PreservedRegsSizeBytes; |
| 856 uint32_t StackSize = applyStackAlignment(StackOffset + SpillAreaSizeBytes); | 854 uint32_t StackSize = applyStackAlignment(StackOffset + SpillAreaSizeBytes); |
| 857 StackSize = applyStackAlignment(StackSize + MaxOutArgsSizeBytes); | 855 StackSize = applyStackAlignment(StackSize + MaxOutArgsSizeBytes); |
| 858 SpillAreaSizeBytes = StackSize - StackOffset; | 856 SpillAreaSizeBytes = StackSize - StackOffset; |
| 857 } else { |
| 858 SpillAreaSizeBytes += MaxOutArgsSizeBytes; |
| 859 } | 859 } |
| 860 | 860 |
| 861 // Combine fixed alloca with SpillAreaSize. | 861 // Combine fixed alloca with SpillAreaSize. |
| 862 SpillAreaSizeBytes += FixedAllocaSizeBytes; | 862 SpillAreaSizeBytes += FixedAllocaSizeBytes; |
| 863 | 863 |
| 864 // Generate "sub sp, SpillAreaSizeBytes" | 864 // Generate "sub sp, SpillAreaSizeBytes" |
| 865 if (SpillAreaSizeBytes) { | 865 if (SpillAreaSizeBytes) { |
| 866 // Use the scratch register if needed to legalize the immediate. | 866 // Use the scratch register if needed to legalize the immediate. |
| 867 Operand *SubAmount = legalize(Ctx->getConstantInt32(SpillAreaSizeBytes), | 867 Operand *SubAmount = legalize(Ctx->getConstantInt32(SpillAreaSizeBytes), |
| 868 Legal_Reg | Legal_Flex, getReservedTmpReg()); | 868 Legal_Reg | Legal_Flex, getReservedTmpReg()); |
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| 5730 // Technically R9 is used for TLS with Sandboxing, and we reserve it. | 5730 // Technically R9 is used for TLS with Sandboxing, and we reserve it. |
| 5731 // However, for compatibility with current NaCl LLVM, don't claim that. | 5731 // However, for compatibility with current NaCl LLVM, don't claim that. |
| 5732 Str << ".eabi_attribute 14, 3 @ Tag_ABI_PCS_R9_use: Not used\n"; | 5732 Str << ".eabi_attribute 14, 3 @ Tag_ABI_PCS_R9_use: Not used\n"; |
| 5733 } | 5733 } |
| 5734 | 5734 |
| 5735 llvm::SmallBitVector TargetARM32::TypeToRegisterSet[IceType_NUM]; | 5735 llvm::SmallBitVector TargetARM32::TypeToRegisterSet[IceType_NUM]; |
| 5736 llvm::SmallBitVector TargetARM32::RegisterAliases[RegARM32::Reg_NUM]; | 5736 llvm::SmallBitVector TargetARM32::RegisterAliases[RegARM32::Reg_NUM]; |
| 5737 llvm::SmallBitVector TargetARM32::ScratchRegs; | 5737 llvm::SmallBitVector TargetARM32::ScratchRegs; |
| 5738 | 5738 |
| 5739 } // end of namespace Ice | 5739 } // end of namespace Ice |
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