Unify alloca, outgoing arg, and prolog construction

src/IceAssemblerARM32.cpp

 //===- subzero/src/IceAssemblerARM32.cpp - Assembler for ARM32 --*- C++ -*-===//
 //
 // Copyright (c) 2013, the Dart project authors.  Please see the AUTHORS file
 // for details. All rights reserved. Use of this source code is governed by a
 // BSD-style license that can be found in the LICENSE file.
 //
 // Modified by the Subzero authors.
 //
 //===----------------------------------------------------------------------===//
 //
@@ skipping 278 matching lines @@
                             const AssemblerARM32::TargetInfo &TInfo) {
   Value = 0; // Make sure initialized.
   if (const auto *Var = llvm::dyn_cast<Variable>(Opnd)) {
     // Should be a stack variable, with an offset.
     if (Var->hasReg())
       return CantDecode;
     IOffsetT Offset = Var->getStackOffset();
     if (!Utils::IsAbsoluteUint(12, Offset))
       return CantDecode;
     int32_t BaseRegNum = Var->getBaseRegNum();
-    if (BaseRegNum == Variable::NoRegister) {
+    if (BaseRegNum == Variable::NoRegister)
       BaseRegNum = TInfo.FrameOrStackReg;
-      if (!TInfo.HasFramePointer)
-        Offset += TInfo.StackAdjustment;
-    }
     Value = decodeImmRegOffset(decodeGPRRegister(BaseRegNum), Offset,
                                OperandARM32Mem::Offset);
     return DecodedAsImmRegOffset;
   }
   if (const auto *Mem = llvm::dyn_cast<OperandARM32Mem>(Opnd)) {
     Variable *Var = Mem->getBase();
     if (!Var->hasReg())
       return CantDecode;
     IValueT Rn = Var->getRegNum();
     if (Mem->isRegReg()) {
@@ skipping 1095 matching lines @@
     // rr defined (RotationValue) rotate.
     constexpr IValueT Opcode = B26 | B25 | B23 | B22 | B21 | B20;
     emitUxt(Cond, Opcode, Rd, Rn, Rm, Rotation);
     return;
   }
   }
 }
 
 } // end of namespace ARM32
 } // end of namespace Ice