[turbofan] No prespill when having sufficient registers

src/compiler/register-allocator.cc

Index: src/compiler/register-allocator.cc
diff --git a/src/compiler/register-allocator.cc b/src/compiler/register-allocator.cc
index fdd2538089cf521adb74b9620a44fb9e83f56326..65dadddda3ad368e417ded8330e87a7841190d72 100644
--- a/src/compiler/register-allocator.cc
+++ b/src/compiler/register-allocator.cc
@@ -2432,7 +2432,8 @@ void LinearScanAllocator::AllocateRegisters() {
   DCHECK(active_live_ranges().empty());
   DCHECK(inactive_live_ranges().empty());
 
-  SplitAndSpillRangesDefinedByMemoryOperand(false);
+  SplitAndSpillRangesDefinedByMemoryOperand(code()->VirtualRegisterCount() <=
+                                            num_allocatable_registers());

[Jarin, 2015/11/24 10:17:36]

This seems to be a hacky approximation in both directions:

- if there seem to be enough allocatable registers, they can still be eaten by
fixed/temp register uses.
- if there are too many virtual registers, they might not be alive at the same
time.

I would like to understand what exactly is the problem. Could not we fix
SplitAndSpillRangesDefinedByMemoryOperand function to behave a bit better? For
example, it seems to me that if the next non-register use is in deferred code,
we would still decide to spill. Also if there is no use at all, we seem to
prefer spilling.

 
   for (TopLevelLiveRange* range : data()->live_ranges()) {
     if (!CanProcessRange(range)) continue;