[turbofan] No prespill when having sufficient registers

We can avoid spilling live ranges with spill ranges when we have
sufficient physical registers for all the virtual registers.

This should come in handy for frame elision. There, I noticed that even
for very small functions (==very few virtual registers), because we spill
the context/function marker ranges, we lose the frame elision
opportunity.

There is a subsequent change needed to fully help frame elision -
decoupling spilling of context & function marker from prologue.

BUG=

Committed: https://crrev.com/c3e6048cdee9cc289f472e205ca7058c654e2f7c
Cr-Commit-Position: refs/heads/master@{#32221}

[Mircea Trofin, 2015-11-23 05:37:39]

Description was changed from

==========
Do not prespill when having sufficient registers

BUG=
==========

to

==========
We can avoid spilling live ranges with spill ranges when we have 
sufficient physical registers for all the virtual registers.

This should come in handy for frame elision. There, I noticed that even 
for very small functions (==very few virtual registers), because we spill 
the context/function marker ranges, we lose the frame elision 
opportunity.

There is a subsequent change needed to fully help frame elision -
decoupling spilling of context & function marker from prologue.

BUG=
==========

[Mircea Trofin, 2015-11-23 05:37:39]

mtrofin@chromium.org changed reviewers:
+ bmeurer@chromium.org, jarin@chromium.org

[Jarin, 2015-11-24 10:17:36]

lgtm, although it seems we should do better, somehow.

https://codereview.chromium.org/1469743002/diff/1/src/compiler/register-alloc...
File src/compiler/register-allocator.cc (right):

https://codereview.chromium.org/1469743002/diff/1/src/compiler/register-alloc...
src/compiler/register-allocator.cc:2436: num_allocatable_registers());
This seems to be a hacky approximation in both directions:

- if there seem to be enough allocatable registers, they can still be eaten by
fixed/temp register uses.
- if there are too many virtual registers, they might not be alive at the same
time.

I would like to understand what exactly is the problem. Could not we fix
SplitAndSpillRangesDefinedByMemoryOperand function to behave a bit better? For
example, it seems to me that if the next non-register use is in deferred code,
we would still decide to spill. Also if there is no use at all, we seem to
prefer spilling.

[Mircea Trofin, 2015-11-24 16:18:40]

The CQ bit was checked by mtrofin@chromium.org

[commit-bot: I haz the power, 2015-11-24 16:18:56]

CQ is trying da patch. Follow status at
 https://chromium-cq-status.appspot.com/patch-status/1469743002/1
View timeline at
 https://chromium-cq-status.appspot.com/patch-timeline/1469743002/1

[Mircea Trofin, 2015-11-24 16:25:34]

On 2015/11/24 10:17:36, Jarin wrote:
> lgtm, although it seems we should do better, somehow.
> 
>
https://codereview.chromium.org/1469743002/diff/1/src/compiler/register-alloc...
> File src/compiler/register-allocator.cc (right):
> 
>
https://codereview.chromium.org/1469743002/diff/1/src/compiler/register-alloc...
> src/compiler/register-allocator.cc:2436: num_allocatable_registers());
> This seems to be a hacky approximation in both directions:
> 
> - if there seem to be enough allocatable registers, they can still be eaten by
> fixed/temp register uses.
> - if there are too many virtual registers, they might not be alive at the same
> time.
> 
> I would like to understand what exactly is the problem. Could not we fix
> SplitAndSpillRangesDefinedByMemoryOperand function to behave a bit better? For
> example, it seems to me that if the next non-register use is in deferred code,
> we would still decide to spill. Also if there is no use at all, we seem to
> prefer spilling.

I agree - thanks for the suggestions. I'll get this in first so I can have at
least some cases where we don't preemptively spill the context and function
marker live ranges (which is the specific problem I was trying to nail down).

Opened v8:4571 to track this.

[commit-bot: I haz the power, 2015-11-24 16:47:57]

Committed patchset #1 (id:1)

[commit-bot: I haz the power, 2015-11-24 16:48:11]

Patchset 1 (id:??) landed as
https://crrev.com/c3e6048cdee9cc289f472e205ca7058c654e2f7c
Cr-Commit-Position: refs/heads/master@{#32221}