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Side by Side Diff: src/IceTargetLoweringARM32.h

Issue 1469113003: Subzero. ARM32. Strength reduce multiplications. (Closed) Base URL: https://chromium.googlesource.com/native_client/pnacl-subzero.git@master
Patch Set: Addresses comments. Created 5 years ago
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1 //===- subzero/src/IceTargetLoweringARM32.h - ARM32 lowering ----*- C++ -*-===// 1 //===- subzero/src/IceTargetLoweringARM32.h - ARM32 lowering ----*- C++ -*-===//
2 // 2 //
3 // The Subzero Code Generator 3 // The Subzero Code Generator
4 // 4 //
5 // This file is distributed under the University of Illinois Open Source 5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details. 6 // License. See LICENSE.TXT for details.
7 // 7 //
8 //===----------------------------------------------------------------------===// 8 //===----------------------------------------------------------------------===//
9 /// 9 ///
10 /// \file 10 /// \file
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970 970
971 using BoolComputationMap = std::unordered_map<SizeT, BoolComputationEntry>; 971 using BoolComputationMap = std::unordered_map<SizeT, BoolComputationEntry>;
972 BoolComputationMap KnownComputations; 972 BoolComputationMap KnownComputations;
973 }; 973 };
974 974
975 BoolComputationTracker BoolComputations; 975 BoolComputationTracker BoolComputations;
976 976
977 // AllowTemporaryWithNoReg indicates if TargetARM32::makeReg() can be invoked 977 // AllowTemporaryWithNoReg indicates if TargetARM32::makeReg() can be invoked
978 // without specifying a physical register. This is needed for creating unbound 978 // without specifying a physical register. This is needed for creating unbound
979 // temporaries during Ice -> ARM lowering, but before register allocation. 979 // temporaries during Ice -> ARM lowering, but before register allocation.
980 // This a safe-guard that, during the legalization post-passes no unbound 980 // This a safe-guard that no unbound temporaries are created during the
981 // temporaries are created. 981 // legalization post-passes.
982 bool AllowTemporaryWithNoReg = true; 982 bool AllowTemporaryWithNoReg = true;
983 // ForbidTemporaryWithoutReg is a RAII class that manages 983 // ForbidTemporaryWithoutReg is a RAII class that manages
984 // AllowTemporaryWithNoReg. 984 // AllowTemporaryWithNoReg.
985 class ForbidTemporaryWithoutReg { 985 class ForbidTemporaryWithoutReg {
986 ForbidTemporaryWithoutReg() = delete; 986 ForbidTemporaryWithoutReg() = delete;
987 ForbidTemporaryWithoutReg(const ForbidTemporaryWithoutReg&) = delete; 987 ForbidTemporaryWithoutReg(const ForbidTemporaryWithoutReg &) = delete;
988 ForbidTemporaryWithoutReg &operator=(const ForbidTemporaryWithoutReg&) = del ete; 988 ForbidTemporaryWithoutReg &
989 operator=(const ForbidTemporaryWithoutReg &) = delete;
989 990
990 public: 991 public:
991 explicit ForbidTemporaryWithoutReg(TargetARM32 *Target) : Target(Target) { 992 explicit ForbidTemporaryWithoutReg(TargetARM32 *Target) : Target(Target) {
992 Target->AllowTemporaryWithNoReg = false; 993 Target->AllowTemporaryWithNoReg = false;
993 } 994 }
994 ~ForbidTemporaryWithoutReg() { Target->AllowTemporaryWithNoReg = true; } 995 ~ForbidTemporaryWithoutReg() { Target->AllowTemporaryWithNoReg = true; }
995 996
996 private: 997 private:
997 TargetARM32 *const Target; 998 TargetARM32 *const Target;
998 }; 999 };
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1037 1038
1038 private: 1039 private:
1039 ~TargetHeaderARM32() = default; 1040 ~TargetHeaderARM32() = default;
1040 1041
1041 TargetARM32Features CPUFeatures; 1042 TargetARM32Features CPUFeatures;
1042 }; 1043 };
1043 1044
1044 } // end of namespace Ice 1045 } // end of namespace Ice
1045 1046
1046 #endif // SUBZERO_SRC_ICETARGETLOWERINGARM32_H 1047 #endif // SUBZERO_SRC_ICETARGETLOWERINGARM32_H
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