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Issue 1467473003: Subzero. ARM32. No more SP frobbing. (Closed) Base URL: https://chromium.googlesource.com/native_client/pnacl-subzero.git@master
Patch Set: Fixes the Offsetis typo. Created 5 years, 1 month ago
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« src/IceTargetLoweringARM32.cpp ('K') | « src/IceTargetLoweringX86Base.h ('k') | tests_lit/llvm2ice_tests/large_stack_offs.ll » ('j') | no next file with comments »
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1 ; This tries to be a comprehensive test of i64 operations, in 1 ; This tries to be a comprehensive test of i64 operations, in
2 ; particular the patterns for lowering i64 operations into constituent 2 ; particular the patterns for lowering i64 operations into constituent
3 ; i32 operations on x86-32. 3 ; i32 operations on x86-32.
4 4
5 ; RUN: %if --need=target_X8632 --command %p2i --filetype=obj --disassemble \ 5 ; RUN: %if --need=target_X8632 --command %p2i --filetype=obj --disassemble \
6 ; RUN: --target x8632 -i %s --args -O2 -allow-externally-defined-symbols \ 6 ; RUN: --target x8632 -i %s --args -O2 -allow-externally-defined-symbols \
7 ; RUN: | %if --need=target_X8632 --command FileCheck %s 7 ; RUN: | %if --need=target_X8632 --command FileCheck %s
8 8
9 ; RUN: %if --need=target_X8632 --command %p2i --filetype=obj --disassemble \ 9 ; RUN: %if --need=target_X8632 --command %p2i --filetype=obj --disassemble \
10 ; RUN: --target x8632 -i %s --args -Om1 -allow-externally-defined-symbols \ 10 ; RUN: --target x8632 -i %s --args -Om1 -allow-externally-defined-symbols \
(...skipping 74 matching lines...) Expand 10 before | Expand all | Expand 10 after
85 ; OPTM1: call {{.*}} R_{{.*}} ignore64BitArgNoInline 85 ; OPTM1: call {{.*}} R_{{.*}} ignore64BitArgNoInline
86 ; OPTM1: sub esp 86 ; OPTM1: sub esp
87 ; OPTM1: mov DWORD PTR [esp+0x4] 87 ; OPTM1: mov DWORD PTR [esp+0x4]
88 ; OPTM1: mov DWORD PTR [esp] 88 ; OPTM1: mov DWORD PTR [esp]
89 ; OPTM1: mov DWORD PTR [esp+0x8],0x7b 89 ; OPTM1: mov DWORD PTR [esp+0x8],0x7b
90 ; OPTM1: mov DWORD PTR [esp+0x10] 90 ; OPTM1: mov DWORD PTR [esp+0x10]
91 ; OPTM1: mov DWORD PTR [esp+0xc] 91 ; OPTM1: mov DWORD PTR [esp+0xc]
92 ; OPTM1: call {{.*}} R_{{.*}} ignore64BitArgNoInline 92 ; OPTM1: call {{.*}} R_{{.*}} ignore64BitArgNoInline
93 93
94 ; ARM32-LABEL: pass64BitArg 94 ; ARM32-LABEL: pass64BitArg
95 ; ARM32: sub sp, {{.*}} #16
96 ; ARM32: str {{.*}}, [sp] 95 ; ARM32: str {{.*}}, [sp]
97 ; ARM32: movw r2, #123 96 ; ARM32: movw r2, #123
98 ; ARM32: bl {{.*}} ignore64BitArgNoInline 97 ; ARM32: bl {{.*}} ignore64BitArgNoInline
99 ; ARM32: add sp, {{.*}} #16
100 ; ARM32: sub sp, {{.*}} #16
101 ; ARM32: str {{.*}}, [sp] 98 ; ARM32: str {{.*}}, [sp]
102 ; ARM32: {{mov|ldr}} r0 99 ; ARM32: {{mov|ldr}} r0
103 ; ARM32: {{mov|ldr}} r1 100 ; ARM32: {{mov|ldr}} r1
104 ; ARM32: movw r2, #123 101 ; ARM32: movw r2, #123
105 ; ARM32: bl {{.*}} ignore64BitArgNoInline 102 ; ARM32: bl {{.*}} ignore64BitArgNoInline
106 ; ARM32: add sp, {{.*}} #16
107 ; ARM32: sub sp, {{.*}} #16
108 ; ARM32: str {{.*}}, [sp] 103 ; ARM32: str {{.*}}, [sp]
109 ; ARM32: {{mov|ldr}} r0 104 ; ARM32: {{mov|ldr}} r0
110 ; ARM32: {{mov|ldr}} r1 105 ; ARM32: {{mov|ldr}} r1
111 ; ARM32: movw r2, #123 106 ; ARM32: movw r2, #123
112 ; ARM32: bl {{.*}} ignore64BitArgNoInline 107 ; ARM32: bl {{.*}} ignore64BitArgNoInline
113 ; ARM32: add sp, {{.*}} #16
114 108
115 109
116 declare i32 @ignore64BitArgNoInline(i64, i32, i64) 110 declare i32 @ignore64BitArgNoInline(i64, i32, i64)
117 111
118 define internal i32 @pass64BitConstArg(i64 %a, i64 %b) { 112 define internal i32 @pass64BitConstArg(i64 %a, i64 %b) {
119 entry: 113 entry:
120 %call = call i32 @ignore64BitArgNoInline(i64 %b, i32 123, i64 -240105309230672 5256) 114 %call = call i32 @ignore64BitArgNoInline(i64 %b, i32 123, i64 -240105309230672 5256)
121 ret i32 %call 115 ret i32 %call
122 } 116 }
123 ; CHECK-LABEL: pass64BitConstArg 117 ; CHECK-LABEL: pass64BitConstArg
(...skipping 13 matching lines...) Expand all
137 ; OPTM1: mov DWORD PTR [esp+0x4] 131 ; OPTM1: mov DWORD PTR [esp+0x4]
138 ; OPTM1-NEXT: mov DWORD PTR [esp] 132 ; OPTM1-NEXT: mov DWORD PTR [esp]
139 ; OPTM1-NEXT: mov DWORD PTR [esp+0x8],0x7b 133 ; OPTM1-NEXT: mov DWORD PTR [esp+0x8],0x7b
140 ; Bundle padding might be added (so not using -NEXT). 134 ; Bundle padding might be added (so not using -NEXT).
141 ; OPTM1: mov DWORD PTR [esp+0x10],0xdeadbeef 135 ; OPTM1: mov DWORD PTR [esp+0x10],0xdeadbeef
142 ; OPTM1-NEXT: mov DWORD PTR [esp+0xc],0x12345678 136 ; OPTM1-NEXT: mov DWORD PTR [esp+0xc],0x12345678
143 ; OPTM1-NOT: mov 137 ; OPTM1-NOT: mov
144 ; OPTM1: call {{.*}} R_{{.*}} ignore64BitArgNoInline 138 ; OPTM1: call {{.*}} R_{{.*}} ignore64BitArgNoInline
145 139
146 ; ARM32-LABEL: pass64BitConstArg 140 ; ARM32-LABEL: pass64BitConstArg
147 ; ARM32: sub sp, {{.*}} #16
148 ; ARM32: movw [[REG1:r.*]], {{.*}} ; 0xbeef 141 ; ARM32: movw [[REG1:r.*]], {{.*}} ; 0xbeef
149 ; ARM32: movt [[REG1]], {{.*}} ; 0xdead 142 ; ARM32: movt [[REG1]], {{.*}} ; 0xdead
150 ; ARM32: movw [[REG2:r.*]], {{.*}} ; 0x5678 143 ; ARM32: movw [[REG2:r.*]], {{.*}} ; 0x5678
151 ; ARM32: movt [[REG2]], {{.*}} ; 0x1234 144 ; ARM32: movt [[REG2]], {{.*}} ; 0x1234
152 ; ARM32: str [[REG1]], [sp, #4] 145 ; ARM32: str [[REG1]], [sp, #4]
153 ; ARM32: str [[REG2]], [sp] 146 ; ARM32: str [[REG2]], [sp]
154 ; ARM32: {{mov|ldr}} r0 147 ; ARM32: {{mov|ldr}} r0
155 ; ARM32: {{mov|ldr}} r1 148 ; ARM32: {{mov|ldr}} r1
156 ; ARM32: movw r2, #123 149 ; ARM32: movw r2, #123
157 ; ARM32: bl {{.*}} ignore64BitArgNoInline 150 ; ARM32: bl {{.*}} ignore64BitArgNoInline
158 ; ARM32: add sp, {{.*}} #16
159 151
160 define internal i32 @pass64BitUndefArg() { 152 define internal i32 @pass64BitUndefArg() {
161 entry: 153 entry:
162 %call = call i32 @ignore64BitArgNoInline(i64 0, i32 123, i64 undef) 154 %call = call i32 @ignore64BitArgNoInline(i64 0, i32 123, i64 undef)
163 ret i32 %call 155 ret i32 %call
164 } 156 }
165 ; CHECK-LABEL: pass64BitUndefArg 157 ; CHECK-LABEL: pass64BitUndefArg
166 ; CHECK: sub esp 158 ; CHECK: sub esp
167 ; CHECK: mov DWORD PTR{{.*}},0x7b 159 ; CHECK: mov DWORD PTR{{.*}},0x7b
168 ; CHECK: mov DWORD PTR{{.*}},0x0 160 ; CHECK: mov DWORD PTR{{.*}},0x0
(...skipping 1689 matching lines...) Expand 10 before | Expand all | Expand 10 after
1858 ; CHECK-LABEL: phi64Undef 1850 ; CHECK-LABEL: phi64Undef
1859 ; CHECK: mov {{.*}},0x0 1851 ; CHECK: mov {{.*}},0x0
1860 ; CHECK: mov {{.*}},0x0 1852 ; CHECK: mov {{.*}},0x0
1861 ; OPTM1-LABEL: phi64Undef 1853 ; OPTM1-LABEL: phi64Undef
1862 ; OPTM1: mov {{.*}},0x0 1854 ; OPTM1: mov {{.*}},0x0
1863 ; OPTM1: mov {{.*}},0x0 1855 ; OPTM1: mov {{.*}},0x0
1864 ; ARM32-LABEL: phi64Undef 1856 ; ARM32-LABEL: phi64Undef
1865 ; ARM32: mov {{.*}} #0 1857 ; ARM32: mov {{.*}} #0
1866 ; ARM32: mov {{.*}} #0 1858 ; ARM32: mov {{.*}} #0
1867 1859
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« src/IceTargetLoweringARM32.cpp ('K') | « src/IceTargetLoweringX86Base.h ('k') | tests_lit/llvm2ice_tests/large_stack_offs.ll » ('j') | no next file with comments »

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