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| 1 //===- subzero/src/IceInstARM32.cpp - ARM32 instruction implementation ----===// | 1 //===- subzero/src/IceInstARM32.cpp - ARM32 instruction implementation ----===// |
| 2 // | 2 // |
| 3 // The Subzero Code Generator | 3 // The Subzero Code Generator |
| 4 // | 4 // |
| 5 // This file is distributed under the University of Illinois Open Source | 5 // This file is distributed under the University of Illinois Open Source |
| 6 // License. See LICENSE.TXT for details. | 6 // License. See LICENSE.TXT for details. |
| 7 // | 7 // |
| 8 //===----------------------------------------------------------------------===// | 8 //===----------------------------------------------------------------------===// |
| 9 /// | 9 /// |
| 10 /// \file | 10 /// \file |
| (...skipping 364 matching lines...) Expand 10 before | Expand all | Expand 10 after Loading... |
| 375 NumVars = 1; | 375 NumVars = 1; |
| 376 Variable *ShiftVar = llvm::dyn_cast_or_null<Variable>(ShiftAmt); | 376 Variable *ShiftVar = llvm::dyn_cast_or_null<Variable>(ShiftAmt); |
| 377 if (ShiftVar) | 377 if (ShiftVar) |
| 378 ++NumVars; | 378 ++NumVars; |
| 379 Vars = Func->allocateArrayOf<Variable *>(NumVars); | 379 Vars = Func->allocateArrayOf<Variable *>(NumVars); |
| 380 Vars[0] = Reg; | 380 Vars[0] = Reg; |
| 381 if (ShiftVar) | 381 if (ShiftVar) |
| 382 Vars[1] = ShiftVar; | 382 Vars[1] = ShiftVar; |
| 383 } | 383 } |
| 384 | 384 |
| 385 InstARM32AdjustStack::InstARM32AdjustStack(Cfg *Func, Variable *SP, | |
| 386 SizeT Amount, Operand *SrcAmount) | |
| 387 : InstARM32(Func, InstARM32::Adjuststack, 2, SP), Amount(Amount) { | |
| 388 addSource(SP); | |
| 389 addSource(SrcAmount); | |
| 390 } | |
| 391 | |
| 392 InstARM32Br::InstARM32Br(Cfg *Func, const CfgNode *TargetTrue, | 385 InstARM32Br::InstARM32Br(Cfg *Func, const CfgNode *TargetTrue, |
| 393 const CfgNode *TargetFalse, | 386 const CfgNode *TargetFalse, |
| 394 const InstARM32Label *Label, CondARM32::Cond Pred) | 387 const InstARM32Label *Label, CondARM32::Cond Pred) |
| 395 : InstARM32Pred(Func, InstARM32::Br, 0, nullptr, Pred), | 388 : InstARM32Pred(Func, InstARM32::Br, 0, nullptr, Pred), |
| 396 TargetTrue(TargetTrue), TargetFalse(TargetFalse), Label(Label) {} | 389 TargetTrue(TargetTrue), TargetFalse(TargetFalse), Label(Label) {} |
| 397 | 390 |
| 398 bool InstARM32Br::optimizeBranch(const CfgNode *NextNode) { | 391 bool InstARM32Br::optimizeBranch(const CfgNode *NextNode) { |
| 399 // If there is no next block, then there can be no fallthrough to optimize. | 392 // If there is no next block, then there can be no fallthrough to optimize. |
| 400 if (NextNode == nullptr) | 393 if (NextNode == nullptr) |
| 401 return false; | 394 return false; |
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| 1265 Ostream &Str = Func->getContext()->getStrDump(); | 1258 Ostream &Str = Func->getContext()->getStrDump(); |
| 1266 Str << "pop" | 1259 Str << "pop" |
| 1267 << " "; | 1260 << " "; |
| 1268 for (SizeT I = 0; I < Dests.size(); ++I) { | 1261 for (SizeT I = 0; I < Dests.size(); ++I) { |
| 1269 if (I > 0) | 1262 if (I > 0) |
| 1270 Str << ", "; | 1263 Str << ", "; |
| 1271 Dests[I]->dump(Func); | 1264 Dests[I]->dump(Func); |
| 1272 } | 1265 } |
| 1273 } | 1266 } |
| 1274 | 1267 |
| 1275 void InstARM32AdjustStack::emit(const Cfg *Func) const { | |
| 1276 if (!BuildDefs::dump()) | |
| 1277 return; | |
| 1278 Ostream &Str = Func->getContext()->getStrEmit(); | |
| 1279 assert(getSrcSize() == 2); | |
| 1280 Str << "\t" | |
| 1281 << "sub" | |
| 1282 << "\t"; | |
| 1283 getDest()->emit(Func); | |
| 1284 Str << ", "; | |
| 1285 getSrc(0)->emit(Func); | |
| 1286 Str << ", "; | |
| 1287 getSrc(1)->emit(Func); | |
| 1288 Func->getTarget()->updateStackAdjustment(Amount); | |
| 1289 } | |
| 1290 | |
| 1291 void InstARM32AdjustStack::dump(const Cfg *Func) const { | |
| 1292 if (!BuildDefs::dump()) | |
| 1293 return; | |
| 1294 Ostream &Str = Func->getContext()->getStrDump(); | |
| 1295 getDest()->dump(Func); | |
| 1296 Str << " = sub.i32 "; | |
| 1297 getSrc(0)->dump(Func); | |
| 1298 Str << ", " << Amount << " ; "; | |
| 1299 getSrc(1)->dump(Func); | |
| 1300 } | |
| 1301 | |
| 1302 void InstARM32Push::emit(const Cfg *Func) const { | 1268 void InstARM32Push::emit(const Cfg *Func) const { |
| 1303 // TODO(jpp): Improve FP register save/restore. | 1269 // TODO(jpp): Improve FP register save/restore. |
| 1304 if (!BuildDefs::dump()) | 1270 if (!BuildDefs::dump()) |
| 1305 return; | 1271 return; |
| 1306 SizeT IntegerCount = 0; | 1272 SizeT IntegerCount = 0; |
| 1307 for (SizeT i = 0; i < getSrcSize(); ++i) { | 1273 for (SizeT i = 0; i < getSrcSize(); ++i) { |
| 1308 if (isScalarIntegerType(getSrc(i)->getType())) { | 1274 if (isScalarIntegerType(getSrc(i)->getType())) { |
| 1309 ++IntegerCount; | 1275 ++IntegerCount; |
| 1310 } | 1276 } |
| 1311 } | 1277 } |
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| 1925 template class InstARM32UnaryopFP<InstARM32::Vsqrt>; | 1891 template class InstARM32UnaryopFP<InstARM32::Vsqrt>; |
| 1926 | 1892 |
| 1927 template class InstARM32FourAddrGPR<InstARM32::Mla>; | 1893 template class InstARM32FourAddrGPR<InstARM32::Mla>; |
| 1928 template class InstARM32FourAddrGPR<InstARM32::Mls>; | 1894 template class InstARM32FourAddrGPR<InstARM32::Mls>; |
| 1929 | 1895 |
| 1930 template class InstARM32CmpLike<InstARM32::Cmn>; | 1896 template class InstARM32CmpLike<InstARM32::Cmn>; |
| 1931 template class InstARM32CmpLike<InstARM32::Cmp>; | 1897 template class InstARM32CmpLike<InstARM32::Cmp>; |
| 1932 template class InstARM32CmpLike<InstARM32::Tst>; | 1898 template class InstARM32CmpLike<InstARM32::Tst>; |
| 1933 | 1899 |
| 1934 } // end of namespace Ice | 1900 } // end of namespace Ice |
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