Subzero. ARM32. No more SP frobbing.

src/IceTargetLoweringARM32.h

 //===- subzero/src/IceTargetLoweringARM32.h - ARM32 lowering ----*- C++ -*-===//
 //
 //                        The Subzero Code Generator
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 ///
 /// \file
@@ skipping 270 matching lines @@
   void _adds(Variable *Dest, Variable *Src0, Operand *Src1,
              CondARM32::Cond Pred = CondARM32::AL) {
     constexpr bool SetFlags = true;
     Context.insert(
         InstARM32Add::create(Func, Dest, Src0, Src1, Pred, SetFlags));
   }
   void _adc(Variable *Dest, Variable *Src0, Operand *Src1,
             CondARM32::Cond Pred = CondARM32::AL) {
     Context.insert(InstARM32Adc::create(Func, Dest, Src0, Src1, Pred));
   }
-  void _adjust_stack(int32_t Amount, Operand *SrcAmount) {
-    Context.insert(InstARM32AdjustStack::create(
-        Func, getPhysicalRegister(RegARM32::Reg_sp), Amount, SrcAmount));
-  }
   void _and(Variable *Dest, Variable *Src0, Operand *Src1,
             CondARM32::Cond Pred = CondARM32::AL) {
     Context.insert(InstARM32And::create(Func, Dest, Src0, Src1, Pred));
   }
   void _asr(Variable *Dest, Variable *Src0, Operand *Src1,
             CondARM32::Cond Pred = CondARM32::AL) {
     Context.insert(InstARM32Asr::create(Func, Dest, Src0, Src1, Pred));
   }
   void _bic(Variable *Dest, Variable *Src0, Operand *Src1,
             CondARM32::Cond Pred = CondARM32::AL) {
@@ skipping 500 matching lines @@
     Context.insert(InstARM32Vmul::create(Func, Dest, Src0, Src1));
   }
   void _vsqrt(Variable *Dest, Variable *Src,
               CondARM32::Cond Pred = CondARM32::AL) {
     Context.insert(InstARM32Vsqrt::create(Func, Dest, Src, Pred));
   }
   void _vsub(Variable *Dest, Variable *Src0, Variable *Src1) {
     Context.insert(InstARM32Vsub::create(Func, Dest, Src0, Src1));
   }
 
+  // Iterates over the CFG and determines the maximum outgoing stack arguments
+  // bytes. This information is later used during addProlog() do pre-allocate
+  // the outargs area.
+  // TODO(jpp): This could live in the Parser, if we provided a Target-specific
+  // method that the Parser could call.
+  void findMaxStackOutArgsSize();

[sehr, 2015/11/20 20:07:35]

FWIW, I like the idea of making the method that computes a particular call
instruction's size a virtual method.  Something like:
 // Compute the space needed to pass this call's arguments on the stack.
 virtual uint32_t getCallArgumentAreaSize(const InstCall *Call) const = 0;

We can later avoid a separate pass by calling that method from processAllocas.

[John, 2015/11/20 22:17:17]

I added the abstract virtual method, and I am now invoking it from the
findMaxOutArgsByteSize() method.

+
   /// Run a pass through stack variables and ensure that the offsets are legal.
   /// If the offset is not legal, use a new base register that accounts for the
   /// offset, such that the addressing mode offset bits are now legal.
   void legalizeStackSlots();
   /// Returns true if the given Offset can be represented in a ldr/str.
   bool isLegalMemOffset(Type Ty, int32_t Offset) const;
   // Creates a new Base register centered around
-  // [OrigBaseReg, +/- Offset+StackAdjust].
-  Variable *newBaseRegister(int32_t Offset, int32_t StackAdjust,
-                            Variable *OrigBaseReg);
-  /// Creates a new, legal OperandARM32Mem for accessing OrigBase + Offset +
-  /// StackAdjust. The returned mem operand is a legal operand for accessing
-  /// memory that is of type Ty.
+  // [OrigBaseReg, +/- Offset].
+  Variable *newBaseRegister(int32_t Offset, Variable *OrigBaseReg);
+  /// Creates a new, legal OperandARM32Mem for accessing OrigBase + Offset. The
+  /// returned mem operand is a legal operand for accessing memory that is of
+  /// type Ty.
   ///
-  /// If [OrigBaseReg, #Offset+StackAdjust] is encodable, then the method
-  /// returns a Mem operand expressing it. Otherwise,
+  /// If [OrigBaseReg, #Offset] is encodable, then the method returns a Mem
+  /// operand expressing it. Otherwise,
   ///
-  /// if [*NewBaseReg, #Offset+StackAdjust-*NewBaseOffset] is encodable, the
-  /// method will return that. Otherwise,
+  /// if [*NewBaseReg, #Offset-*NewBaseOffset] is encodable, the method will
+  /// return that. Otherwise,
   ///
-  /// a new base register ip=OrigBaseReg+Offset+StackAdjust is created, and the
-  /// method returns [ip, #0].
+  /// a new base register ip=OrigBaseReg+Offsetis created, and the method

[sehr, 2015/11/20 20:07:35]

nit: Offset is

[John, 2015/11/20 22:17:17]

Done.

+  /// returns [ip, #0].
   OperandARM32Mem *createMemOperand(Type Ty, int32_t Offset,
-                                    int32_t StackAdjust, Variable *OrigBaseReg,
+                                    Variable *OrigBaseReg,
                                     Variable **NewBaseReg,
                                     int32_t *NewBaseOffset);
   /// Legalizes Mov if its Source (or Destination) is a spilled Variable. Moves
   /// to memory become store instructions, and moves from memory, loads.
-  void legalizeMov(InstARM32Mov *Mov, int32_t StackAdjust,
-                   Variable *OrigBaseReg, Variable **NewBaseReg,
-                   int32_t *NewBaseOffset);
+  void legalizeMov(InstARM32Mov *Mov, Variable *OrigBaseReg,
+                   Variable **NewBaseReg, int32_t *NewBaseOffset);
 
   TargetARM32Features CPUFeatures;
   bool UsesFramePointer = false;
   bool NeedsStackAlignment = false;
   bool MaybeLeafFunc = true;
   size_t SpillAreaSizeBytes = 0;
+  size_t MaxOutArgsSizeBytes = 0;
   // TODO(jpp): std::array instead of array.
   static llvm::SmallBitVector TypeToRegisterSet[RCARM32_NUM];
   static llvm::SmallBitVector RegisterAliases[RegARM32::Reg_NUM];
   static llvm::SmallBitVector ScratchRegs;
   llvm::SmallBitVector RegsUsed;
   VarList PhysicalRegisters[IceType_NUM];
 
   /// Helper class that understands the Calling Convention and register
   /// assignments. The first few integer type parameters can use r0-r3,
   /// regardless of their position relative to the floating-point/vector
@@ skipping 145 matching lines @@
 
 private:
   ~TargetHeaderARM32() = default;
 
   TargetARM32Features CPUFeatures;
 };
 
 } // end of namespace Ice
 
 #endif // SUBZERO_SRC_ICETARGETLOWERINGARM32_H