Subzero. ARM32. No more SP frobbing.

src/IceTargetLoweringARM32.cpp

 //===- subzero/src/IceTargetLoweringARM32.cpp - ARM32 lowering ------------===//
 //
 //                        The Subzero Code Generator
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 ///
 /// \file
@@ skipping 215 matching lines @@
       continue;
     }
     Lo->setRegNum(FirstReg);
     Lo->setMustHaveReg();
     Hi->setRegNum(FirstReg + 1);
     Hi->setMustHaveReg();
   }
 }
 } // end of anonymous namespace
 
+void TargetARM32::findMaxStackOutArgsSize() {
+  // MinNeededOutArgsBytes should be updated if the Target ever creates an
+  // high-level InstCall that requires more stack bytes.
+  constexpr size_t MinNeededOutArgsBytes = 0;
+  MaxOutArgsSizeBytes = MinNeededOutArgsBytes;
+  for (CfgNode *Node : Func->getNodes()) {
+    Context.init(Node);
+    while (!Context.atEnd()) {

[sehr, 2015/11/20 20:07:35]

Again, factor to call the virtual method here.

[John, 2015/11/20 22:17:17]

Done.

+      PostIncrLoweringContext PostIncrement(Context);
+      Inst *CurInstr = Context.getCur();
+      if (auto *Call = llvm::dyn_cast<InstCall>(CurInstr)) {
+        TargetARM32::CallingConv CC;
+        size_t OutArgsSizeBytes = 0;
+        for (SizeT i = 0, NumArgs = Call->getNumArgs(); i < NumArgs; ++i) {
+          Operand *Arg = legalizeUndef(Call->getArg(i));
+          Type Ty = Arg->getType();
+          if (Ty == IceType_i64) {
+            std::pair<int32_t, int32_t> Regs;
+            if (CC.I64InRegs(&Regs)) {
+              continue;
+            }
+          } else if (isVectorType(Ty) || isFloatingType(Ty)) {
+            int32_t Reg;
+            if (CC.FPInReg(Ty, &Reg)) {
+              continue;
+            }
+          } else {
+            assert(Ty == IceType_i32);
+            int32_t Reg;
+            if (CC.I32InReg(&Reg)) {
+              continue;
+            }
+          }
+
+          OutArgsSizeBytes = applyStackAlignmentTy(OutArgsSizeBytes, Ty);
+          OutArgsSizeBytes += typeWidthInBytesOnStack(Ty);
+        }
+        OutArgsSizeBytes = applyStackAlignment(OutArgsSizeBytes);
+        MaxOutArgsSizeBytes = std::max(MaxOutArgsSizeBytes, OutArgsSizeBytes);
+      }
+    }
+  }
+}
+
 void TargetARM32::translateO2() {
   TimerMarker T(TimerStack::TT_O2, Func);
 
   // TODO(stichnot): share passes with X86?
   // https://code.google.com/p/nativeclient/issues/detail?id=4094
+  findMaxStackOutArgsSize();
 
   // Do not merge Alloca instructions, and lay out the stack.
   static constexpr bool SortAndCombineAllocas = false;
   Func->processAllocas(SortAndCombineAllocas);
   Func->dump("After Alloca processing");
 
   if (!Ctx->getFlags().getPhiEdgeSplit()) {
     // Lower Phi instructions.
     Func->placePhiLoads();
     if (Func->hasError())
@@ skipping 86 matching lines @@
   // Nop insertion
   if (Ctx->getFlags().shouldDoNopInsertion()) {
     Func->doNopInsertion();
   }
 }
 
 void TargetARM32::translateOm1() {
   TimerMarker T(TimerStack::TT_Om1, Func);
 
   // TODO: share passes with X86?
+  findMaxStackOutArgsSize();
 
   // Do not merge Alloca instructions, and lay out the stack.
   static constexpr bool SortAndCombineAllocas = false;
   Func->processAllocas(SortAndCombineAllocas);
   Func->dump("After Alloca processing");
 
   Func->placePhiLoads();
   if (Func->hasError())
     return;
   Func->placePhiStores();
@@ skipping 107 matching lines @@
     return;
   }
   if (Var->mustHaveReg()) {
     llvm::report_fatal_error(
         "Infinite-weight Variable has no register assigned");
   }
   int32_t Offset = Var->getStackOffset();
   int32_t BaseRegNum = Var->getBaseRegNum();
   if (BaseRegNum == Variable::NoRegister) {
     BaseRegNum = getFrameOrStackReg();
-    if (!hasFramePointer())
-      Offset += getStackAdjustment();
   }
   const Type VarTy = Var->getType();
   Str << "[" << getRegName(BaseRegNum, VarTy);
   if (Offset != 0) {
     Str << ", " << getConstantPrefix() << Offset;
   }
   Str << "]";
 }
 
 bool TargetARM32::CallingConv::I64InRegs(std::pair<int32_t, int32_t> *Regs) {
@@ skipping 175 matching lines @@
   // | 2. padding             |
   // +------------------------+ <--- FramePointer (if used)
   // | 3. global spill area   |
   // +------------------------+
   // | 4. padding             |
   // +------------------------+
   // | 5. local spill area    |
   // +------------------------+
   // | 6. padding             |
   // +------------------------+
-  // | 7. allocas             |
+  // | 7. allocas (variable)  |
+  // +------------------------+
+  // | 8. padding             |
+  // +------------------------+
+  // | 9. out args            |
   // +------------------------+ <--- StackPointer
   //
   // The following variables record the size in bytes of the given areas:
   //  * PreservedRegsSizeBytes: area 1
   //  * SpillAreaPaddingBytes:  area 2
   //  * GlobalsSize:            area 3
   //  * GlobalsAndSubsequentPaddingSize: areas 3 - 4
   //  * LocalsSpillAreaSize:    area 5
-  //  * SpillAreaSizeBytes:     areas 2 - 6
+  //  * SpillAreaSizeBytes:     areas 2 - 6, and 9
+  //  * MaxOutArgsSizeBytes:    area 9
+  //
   // Determine stack frame offsets for each Variable without a register
   // assignment.  This can be done as one variable per stack slot.  Or, do
   // coalescing by running the register allocator again with an infinite set of
   // registers (as a side effect, this gives variables a second chance at
   // physical register assignment).
   //
   // A middle ground approach is to leverage sparsity and allocate one block of
   // space on the frame for globals (variables with multi-block lifetime), and
   // one block to share for locals (single-block lifetime).
 
@@ skipping 85 matching lines @@
   assert(LocalsSlotsAlignmentBytes <= SpillAreaAlignmentBytes);
   uint32_t SpillAreaPaddingBytes = 0;
   uint32_t LocalsSlotsPaddingBytes = 0;
   alignStackSpillAreas(PreservedRegsSizeBytes, SpillAreaAlignmentBytes,
                        GlobalsSize, LocalsSlotsAlignmentBytes,
                        &SpillAreaPaddingBytes, &LocalsSlotsPaddingBytes);
   SpillAreaSizeBytes += SpillAreaPaddingBytes + LocalsSlotsPaddingBytes;
   uint32_t GlobalsAndSubsequentPaddingSize =
       GlobalsSize + LocalsSlotsPaddingBytes;
 
-  // Align SP if necessary.
-  if (NeedsStackAlignment) {
+  // Adds the out args space to the stack, and align SP if necessary.
+  if (!NeedsStackAlignment) {
+    SpillAreaSizeBytes += MaxOutArgsSizeBytes;
+  } else {
     uint32_t StackOffset = PreservedRegsSizeBytes;
     uint32_t StackSize = applyStackAlignment(StackOffset + SpillAreaSizeBytes);
+    StackSize = applyStackAlignment(StackSize + MaxOutArgsSizeBytes);
     SpillAreaSizeBytes = StackSize - StackOffset;
   }
 
   // Generate "sub sp, SpillAreaSizeBytes"
   if (SpillAreaSizeBytes) {
     // Use the scratch register if needed to legalize the immediate.
     Operand *SubAmount = legalize(Ctx->getConstantInt32(SpillAreaSizeBytes),
                                   Legal_Reg | Legal_Flex, getReservedTmpReg());
     Variable *SP = getPhysicalRegister(RegARM32::Reg_sp);
     _sub(SP, SP, SubAmount);
   }
   Ctx->statsUpdateFrameBytes(SpillAreaSizeBytes);
 
-  resetStackAdjustment();
-
   // Fill in stack offsets for stack args, and copy args into registers for
   // those that were register-allocated. Args are pushed right to left, so
   // Arg[0] is closest to the stack/frame pointer.
   Variable *FramePtr = getPhysicalRegister(getFrameOrStackReg());
   size_t BasicFrameOffset = PreservedRegsSizeBytes;
   if (!UsesFramePointer)
     BasicFrameOffset += SpillAreaSizeBytes;
 
   const VarList &Args = Func->getArgs();
   size_t InArgsSizeBytes = 0;
@@ skipping 23 matching lines @@
                       UsesFramePointer);
   this->HasComputedFrame = true;
 
   if (BuildDefs::dump() && Func->isVerbose(IceV_Frame)) {
     OstreamLocker _(Func->getContext());
     Ostream &Str = Func->getContext()->getStrDump();
 
     Str << "Stack layout:\n";
     uint32_t SPAdjustmentPaddingSize =
         SpillAreaSizeBytes - LocalsSpillAreaSize -
-        GlobalsAndSubsequentPaddingSize - SpillAreaPaddingBytes;
+        GlobalsAndSubsequentPaddingSize - SpillAreaPaddingBytes -
+        MaxOutArgsSizeBytes;
     Str << " in-args = " << InArgsSizeBytes << " bytes\n"
         << " preserved registers = " << PreservedRegsSizeBytes << " bytes\n"
         << " spill area padding = " << SpillAreaPaddingBytes << " bytes\n"
         << " globals spill area = " << GlobalsSize << " bytes\n"
         << " globals-locals spill areas intermediate padding = "
         << GlobalsAndSubsequentPaddingSize - GlobalsSize << " bytes\n"
         << " locals spill area = " << LocalsSpillAreaSize << " bytes\n"
         << " SP alignment padding = " << SPAdjustmentPaddingSize << " bytes\n";
 
     Str << "Stack details:\n"
         << " SP adjustment = " << SpillAreaSizeBytes << " bytes\n"
         << " spill area alignment = " << SpillAreaAlignmentBytes << " bytes\n"
+        << " outgoing args size = " << MaxOutArgsSizeBytes << " bytes\n"
         << " locals spill area alignment = " << LocalsSlotsAlignmentBytes
         << " bytes\n"
         << " is FP based = " << UsesFramePointer << "\n";
   }
 }
 
 void TargetARM32::addEpilog(CfgNode *Node) {
   InstList &Insts = Node->getInsts();
   InstList::reverse_iterator RI, E;
   for (RI = Insts.rbegin(), E = Insts.rend(); RI != E; ++RI) {
@@ skipping 76 matching lines @@
   _ret(LR, RetValue);
   _bundle_unlock();
   RI->setDeleted();
 }
 
 bool TargetARM32::isLegalMemOffset(Type Ty, int32_t Offset) const {
   constexpr bool ZeroExt = false;
   return OperandARM32Mem::canHoldOffset(Ty, ZeroExt, Offset);
 }
 
-Variable *TargetARM32::newBaseRegister(int32_t OriginalOffset,
-                                       int32_t StackAdjust,
-                                       Variable *OrigBaseReg) {
-  int32_t Offset = OriginalOffset + StackAdjust;
+Variable *TargetARM32::newBaseRegister(int32_t Offset, Variable *OrigBaseReg) {
   // Legalize will likely need a movw/movt combination, but if the top bits are
   // all 0 from negating the offset and subtracting, we could use that instead.
   bool ShouldSub = (-Offset & 0xFFFF0000) == 0;
   if (ShouldSub)
     Offset = -Offset;
   Operand *OffsetVal = legalize(Ctx->getConstantInt32(Offset),
                                 Legal_Reg | Legal_Flex, getReservedTmpReg());
   Variable *ScratchReg = makeReg(IceType_i32, getReservedTmpReg());
   if (ShouldSub)
     _sub(ScratchReg, OrigBaseReg, OffsetVal);
   else
     _add(ScratchReg, OrigBaseReg, OffsetVal);
   return ScratchReg;
 }
 
 OperandARM32Mem *TargetARM32::createMemOperand(Type Ty, int32_t Offset,
-                                               int32_t StackAdjust,
                                                Variable *OrigBaseReg,
                                                Variable **NewBaseReg,
                                                int32_t *NewBaseOffset) {
-  if (isLegalMemOffset(Ty, Offset + StackAdjust)) {
+  if (isLegalMemOffset(Ty, Offset)) {
     return OperandARM32Mem::create(
-        Func, Ty, OrigBaseReg, llvm::cast<ConstantInteger32>(
-                                   Ctx->getConstantInt32(Offset + StackAdjust)),
+        Func, Ty, OrigBaseReg,
+        llvm::cast<ConstantInteger32>(Ctx->getConstantInt32(Offset)),
         OperandARM32Mem::Offset);
   }
 
   if (*NewBaseReg == nullptr) {
-    *NewBaseReg = newBaseRegister(Offset, StackAdjust, OrigBaseReg);
-    *NewBaseOffset = Offset + StackAdjust;
+    *NewBaseReg = newBaseRegister(Offset, OrigBaseReg);
+    *NewBaseOffset = Offset;
   }
 
-  int32_t OffsetDiff = Offset + StackAdjust - *NewBaseOffset;
+  int32_t OffsetDiff = Offset - *NewBaseOffset;
   if (!isLegalMemOffset(Ty, OffsetDiff)) {
-    *NewBaseReg = newBaseRegister(Offset, StackAdjust, OrigBaseReg);
-    *NewBaseOffset = Offset + StackAdjust;
+    *NewBaseReg = newBaseRegister(Offset, OrigBaseReg);
+    *NewBaseOffset = Offset;
     OffsetDiff = 0;
   }
 
   return OperandARM32Mem::create(
       Func, Ty, *NewBaseReg,
       llvm::cast<ConstantInteger32>(Ctx->getConstantInt32(OffsetDiff)),
       OperandARM32Mem::Offset);
 }
 
-void TargetARM32::legalizeMov(InstARM32Mov *MovInstr, int32_t StackAdjust,
-                              Variable *OrigBaseReg, Variable **NewBaseReg,
-                              int32_t *NewBaseOffset) {
+void TargetARM32::legalizeMov(InstARM32Mov *MovInstr, Variable *OrigBaseReg,
+                              Variable **NewBaseReg, int32_t *NewBaseOffset) {
   Variable *Dest = MovInstr->getDest();
   assert(Dest != nullptr);
   Type DestTy = Dest->getType();
   assert(DestTy != IceType_i64);
 
   Operand *Src = MovInstr->getSrc(0);
   Type SrcTy = Src->getType();
   (void)SrcTy;
   assert(SrcTy != IceType_i64);
 
   if (MovInstr->isMultiDest() || MovInstr->isMultiSource())
     return;
 
   bool Legalized = false;
   if (!Dest->hasReg()) {
     auto *const SrcR = llvm::cast<Variable>(Src);
     assert(SrcR->hasReg());
     const int32_t Offset = Dest->getStackOffset();
     // This is a _mov(Mem(), Variable), i.e., a store.
-    _str(SrcR, createMemOperand(DestTy, Offset, StackAdjust, OrigBaseReg,
-                                NewBaseReg, NewBaseOffset),
+    _str(SrcR, createMemOperand(DestTy, Offset, OrigBaseReg, NewBaseReg,
+                                NewBaseOffset),
          MovInstr->getPredicate());
     // _str() does not have a Dest, so we add a fake-def(Dest).
     Context.insert(InstFakeDef::create(Func, Dest));
     Legalized = true;
   } else if (auto *Var = llvm::dyn_cast<Variable>(Src)) {
     if (!Var->hasReg()) {
       const int32_t Offset = Var->getStackOffset();
-      _ldr(Dest, createMemOperand(DestTy, Offset, StackAdjust, OrigBaseReg,
-                                  NewBaseReg, NewBaseOffset),
+      _ldr(Dest, createMemOperand(DestTy, Offset, OrigBaseReg, NewBaseReg,
+                                  NewBaseOffset),
            MovInstr->getPredicate());
       Legalized = true;
     }
   }
 
   if (Legalized) {
     if (MovInstr->isDestRedefined()) {
       _set_dest_redefined();
     }
     MovInstr->setDeleted();
   }
 }
 
 void TargetARM32::legalizeStackSlots() {
   // If a stack variable's frame offset doesn't fit, convert from:
   //   ldr X, OFF[SP]
   // to:
   //   movw/movt TMP, OFF_PART
   //   add TMP, TMP, SP
   //   ldr X, OFF_MORE[TMP]
   //
   // This is safe because we have reserved TMP, and add for ARM does not
   // clobber the flags register.
   Func->dump("Before legalizeStackSlots");
   assert(hasComputedFrame());
   Variable *OrigBaseReg = getPhysicalRegister(getFrameOrStackReg());
-  int32_t StackAdjust = 0;
   // Do a fairly naive greedy clustering for now. Pick the first stack slot
   // that's out of bounds and make a new base reg using the architecture's temp
   // register. If that works for the next slot, then great. Otherwise, create a
   // new base register, clobbering the previous base register. Never share a
   // base reg across different basic blocks. This isn't ideal if local and
   // multi-block variables are far apart and their references are interspersed.
   // It may help to be more coordinated about assign stack slot numbers and may
   // help to assign smaller offsets to higher-weight variables so that they
   // don't depend on this legalization.
   for (CfgNode *Node : Func->getNodes()) {
     Context.init(Node);
     Variable *NewBaseReg = nullptr;
     int32_t NewBaseOffset = 0;
     while (!Context.atEnd()) {
       PostIncrLoweringContext PostIncrement(Context);
       Inst *CurInstr = Context.getCur();
       Variable *Dest = CurInstr->getDest();
 
       // Check if the previous NewBaseReg is clobbered, and reset if needed.
       if ((Dest && NewBaseReg && Dest->hasReg() &&
            Dest->getRegNum() == NewBaseReg->getBaseRegNum()) ||
           llvm::isa<InstFakeKill>(CurInstr)) {
         NewBaseReg = nullptr;
         NewBaseOffset = 0;
       }
 
-      // The stack adjustment only matters if we are using SP instead of FP.
-      if (!hasFramePointer()) {
-        if (auto *AdjInst = llvm::dyn_cast<InstARM32AdjustStack>(CurInstr)) {
-          StackAdjust += AdjInst->getAmount();
-          NewBaseOffset += AdjInst->getAmount();
-          continue;
-        }
-        if (llvm::isa<InstARM32Call>(CurInstr)) {
-          NewBaseOffset -= StackAdjust;
-          StackAdjust = 0;
-          continue;
-        }
-      }
-
       if (auto *MovInstr = llvm::dyn_cast<InstARM32Mov>(CurInstr)) {
-        legalizeMov(MovInstr, StackAdjust, OrigBaseReg, &NewBaseReg,
-                    &NewBaseOffset);
+        legalizeMov(MovInstr, OrigBaseReg, &NewBaseReg, &NewBaseOffset);
       }
     }
   }
 }
 
 Operand *TargetARM32::loOperand(Operand *Operand) {
   assert(Operand->getType() == IceType_i64);
   if (Operand->getType() != IceType_i64)
     return Operand;
   if (auto *Var64On32 = llvm::dyn_cast<Variable64On32>(Operand))
@@ skipping 141 matching lines @@
     // Non-constant sizes need to be adjusted to the next highest multiple of
     // the required alignment at runtime.
     TotalSize = legalize(TotalSize, Legal_Reg | Legal_Flex);
     Variable *T = makeReg(IceType_i32);
     _mov(T, TotalSize);
     Operand *AddAmount = legalize(Ctx->getConstantInt32(Alignment - 1));
     _add(T, T, AddAmount);
     alignRegisterPow2(T, Alignment);
     _sub(SP, SP, T);
   }
-  _mov(Dest, SP);
+  Variable *T = SP;
+  if (MaxOutArgsSizeBytes != 0) {
+    T = makeReg(getPointerType());
+    Operand *OutArgsSizeRF = legalize(
+        Ctx->getConstantInt32(MaxOutArgsSizeBytes), Legal_Reg | Legal_Flex);
+    _add(T, SP, OutArgsSizeRF);
+  }
+  _mov(Dest, T);
 }
 
 void TargetARM32::div0Check(Type Ty, Operand *SrcLo, Operand *SrcHi) {
   if (isGuaranteedNonzeroInt(SrcLo) || isGuaranteedNonzeroInt(SrcHi))
     return;
   Variable *SrcLoReg = legalizeToReg(SrcLo);
   switch (Ty) {
   default:
     llvm::report_fatal_error("Unexpected type");
   case IceType_i8:
@@ skipping 803 matching lines @@
   }
   case InstArithmetic::Xor: {
     Variable *Src0R = Srcs.src0R(this);
     Operand *Src1RF = Srcs.src1RF(this);
     _eor(T, Src0R, Src1RF);
     _mov(Dest, T);
     return;
   }
   case InstArithmetic::Sub: {
     if (Srcs.hasConstOperand()) {
+      // TODO(jpp): lowering Src0R here is wrong -- Src0R it is not guaranteed
+      // to be used.
       Variable *Src0R = Srcs.src0R(this);
       if (Srcs.immediateIsFlexEncodable()) {
         Operand *Src1RF = Srcs.src1RF(this);
         if (Srcs.swappedOperands()) {
           _rsb(T, Src0R, Src1RF);
         } else {
           _sub(T, Src0R, Src1RF);
         }
         _mov(Dest, T);
         return;
@@ skipping 233 matching lines @@
 
   // Assign arguments to registers and stack. Also reserve stack.
   TargetARM32::CallingConv CC;
   // Pair of Arg Operand -> GPR number assignments.
   llvm::SmallVector<std::pair<Operand *, int32_t>,
                     TargetARM32::CallingConv::ARM32_MAX_GPR_ARG> GPRArgs;
   llvm::SmallVector<std::pair<Operand *, int32_t>,
                     TargetARM32::CallingConv::ARM32_MAX_FP_REG_UNITS> FPArgs;
   // Pair of Arg Operand -> stack offset.
   llvm::SmallVector<std::pair<Operand *, int32_t>, 8> StackArgs;
-  int32_t ParameterAreaSizeBytes = 0;
+  size_t ParameterAreaSizeBytes = 0;
 
   // Classify each argument operand according to the location where the
   // argument is passed.
   for (SizeT i = 0, NumArgs = Instr->getNumArgs(); i < NumArgs; ++i) {
     Operand *Arg = legalizeUndef(Instr->getArg(i));
     Type Ty = Arg->getType();
     bool InRegs = false;
     if (Ty == IceType_i64) {
       std::pair<int32_t, int32_t> Regs;
       if (CC.I64InRegs(&Regs)) {
@@ skipping 23 matching lines @@
           applyStackAlignmentTy(ParameterAreaSizeBytes, Ty);
       StackArgs.push_back(std::make_pair(Arg, ParameterAreaSizeBytes));
       ParameterAreaSizeBytes += typeWidthInBytesOnStack(Ty);
     }
   }
 
   // Adjust the parameter area so that the stack is aligned. It is assumed that
   // the stack is already aligned at the start of the calling sequence.
   ParameterAreaSizeBytes = applyStackAlignment(ParameterAreaSizeBytes);
 
-  // Subtract the appropriate amount for the argument area. This also takes
-  // care of setting the stack adjustment during emission.
-  //
-  // TODO: If for some reason the call instruction gets dead-code eliminated
-  // after lowering, we would need to ensure that the pre-call and the
-  // post-call esp adjustment get eliminated as well.
-  if (ParameterAreaSizeBytes) {
-    Operand *SubAmount = legalize(Ctx->getConstantInt32(ParameterAreaSizeBytes),
-                                  Legal_Reg | Legal_Flex);
-    _adjust_stack(ParameterAreaSizeBytes, SubAmount);
+  if (ParameterAreaSizeBytes > MaxOutArgsSizeBytes) {
+    llvm::report_fatal_error("MaxOutArgsSizeBytes is not really a max.");
   }
 
   // Copy arguments that are passed on the stack to the appropriate stack
   // locations.
   Variable *SP = getPhysicalRegister(RegARM32::Reg_sp);
   for (auto &StackArg : StackArgs) {
     ConstantInteger32 *Loc =
         llvm::cast<ConstantInteger32>(Ctx->getConstantInt32(StackArg.second));
     Type Ty = StackArg.first->getType();
     OperandARM32Mem *Addr;
@@ skipping 72 matching lines @@
     // Generate a FakeUse of register arguments so that they do not get dead
     // code eliminated as a result of the FakeKill of scratch registers after
     // the call.
     Context.insert(InstFakeUse::create(Func, Reg));
   }
   Inst *NewCall = InstARM32Call::create(Func, ReturnReg, CallTarget);
   Context.insert(NewCall);
   if (ReturnRegHi)
     Context.insert(InstFakeDef::create(Func, ReturnRegHi));
 
-  // Add the appropriate offset to SP. The call instruction takes care of
-  // resetting the stack offset during emission.
-  if (ParameterAreaSizeBytes) {
-    Operand *AddAmount = legalize(Ctx->getConstantInt32(ParameterAreaSizeBytes),
-                                  Legal_Reg | Legal_Flex);
-    Variable *SP = getPhysicalRegister(RegARM32::Reg_sp);
-    _add(SP, SP, AddAmount);
-  }
-
   // Insert a register-kill pseudo instruction.
   Context.insert(InstFakeKill::create(Func, NewCall));
 
   // Generate a FakeUse to keep the call live if necessary.
   if (Instr->hasSideEffects() && ReturnReg) {
     Inst *FakeUse = InstFakeUse::create(Func, ReturnReg);
     Context.insert(FakeUse);
   }
 
   if (!Dest)
@@ skipping 2869 matching lines @@
   // Technically R9 is used for TLS with Sandboxing, and we reserve it.
   // However, for compatibility with current NaCl LLVM, don't claim that.
   Str << ".eabi_attribute 14, 3   @ Tag_ABI_PCS_R9_use: Not used\n";
 }
 
 llvm::SmallBitVector TargetARM32::TypeToRegisterSet[IceType_NUM];
 llvm::SmallBitVector TargetARM32::RegisterAliases[RegARM32::Reg_NUM];
 llvm::SmallBitVector TargetARM32::ScratchRegs;
 
 } // end of namespace Ice