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Side by Side Diff: runtime/vm/constants_mips.h

Issue 14672037: Implements FPU compare and branching for MIPS simulator, assembler, disassembler. (Closed) Base URL: http://dart.googlecode.com/svn/branches/bleeding_edge/dart/
Patch Set: Created 7 years, 7 months ago
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1 // Copyright (c) 2013, the Dart project authors. Please see the AUTHORS file 1 // Copyright (c) 2013, the Dart project authors. Please see the AUTHORS file
2 // for details. All rights reserved. Use of this source code is governed by a 2 // for details. All rights reserved. Use of this source code is governed by a
3 // BSD-style license that can be found in the LICENSE file. 3 // BSD-style license that can be found in the LICENSE file.
4 4
5 #ifndef VM_CONSTANTS_MIPS_H_ 5 #ifndef VM_CONSTANTS_MIPS_H_
6 #define VM_CONSTANTS_MIPS_H_ 6 #define VM_CONSTANTS_MIPS_H_
7 7
8 #include "platform/assert.h" 8 #include "platform/assert.h"
9 9
10 namespace dart { 10 namespace dart {
(...skipping 231 matching lines...) Expand 10 before | Expand all | Expand 10 after
242 kCop1FnShift = 0, 242 kCop1FnShift = 0,
243 kCop1FnBits = 6, 243 kCop1FnBits = 6,
244 kCop1SubShift = 21, 244 kCop1SubShift = 21,
245 kCop1SubBits = 5, 245 kCop1SubBits = 5,
246 kImmShift = 0, 246 kImmShift = 0,
247 kImmBits = 16, 247 kImmBits = 16,
248 kInstrShift = 0, 248 kInstrShift = 0,
249 kInstrBits = 26, 249 kInstrBits = 26,
250 kBreakCodeShift = 6, 250 kBreakCodeShift = 6,
251 kBreakCodeBits = 20, 251 kBreakCodeBits = 20,
252 kFpuCCShift = 8,
253 kFpuCCBits = 3,
252 254
253 kBranchOffsetMask = 0x0000ffff, 255 kBranchOffsetMask = 0x0000ffff,
254 }; 256 };
255 257
256 258
257 enum Opcode { 259 enum Opcode {
258 SPECIAL = 0, 260 SPECIAL = 0,
259 REGIMM = 1, 261 REGIMM = 1,
260 J = 2, 262 J = 2,
261 JAL = 3, 263 JAL = 3,
(...skipping 109 matching lines...) Expand 10 before | Expand all | Expand 10 after
371 BGEZAL = 17, 373 BGEZAL = 17,
372 BLTZALL = 18, 374 BLTZALL = 18,
373 BGEZALL = 19, 375 BGEZALL = 19,
374 SYNCI = 31, 376 SYNCI = 31,
375 }; 377 };
376 378
377 379
378 enum Cop1Function { 380 enum Cop1Function {
379 COP1_ADD = 0, 381 COP1_ADD = 0,
380 COP1_MOV = 6, 382 COP1_MOV = 6,
383 COP1_C_F = 0b110000,
384 COP1_C_UN = 0b110001,
385 COP1_C_EQ = 0b110010,
386 COP1_C_UEQ = 0b110011,
387 COP1_C_OLT = 0b110100,
388 COP1_C_ULT = 0b110101,
389 COP1_C_OLE = 0b110110,
390 COP1_C_ULE = 0b110111,
381 }; 391 };
382 392
383 enum Cop1Sub { 393 enum Cop1Sub {
384 COP1_MF = 0, 394 COP1_MF = 0,
385 COP1_MT = 4, 395 COP1_MT = 4,
396 COP1_BC = 8,
386 }; 397 };
387 398
388 enum Format { 399 enum Format {
389 FMT_S = 16, 400 FMT_S = 16,
390 FMT_D = 17, 401 FMT_D = 17,
391 FMT_W = 20, 402 FMT_W = 20,
392 FMT_L = 21, 403 FMT_L = 21,
393 FMT_PS = 22, 404 FMT_PS = 22,
394 }; 405 };
395 406
(...skipping 116 matching lines...) Expand 10 before | Expand all | Expand 10 after
512 } 523 }
513 524
514 inline bool HasFormat() const { 525 inline bool HasFormat() const {
515 return (OpcodeField() == COP1) && (Bit(25) == 1); 526 return (OpcodeField() == COP1) && (Bit(25) == 1);
516 } 527 }
517 528
518 inline Format FormatField() const { 529 inline Format FormatField() const {
519 return static_cast<Format>(Bits(kFmtShift, kFmtBits)); 530 return static_cast<Format>(Bits(kFmtShift, kFmtBits));
520 } 531 }
521 532
533 inline int32_t FpuCCField() const {
534 return Bits(kFpuCCShift, kFpuCCBits);
535 }
536
522 // Instructions are read out of a code stream. The only way to get a 537 // Instructions are read out of a code stream. The only way to get a
523 // reference to an instruction is to convert a pc. There is no way 538 // reference to an instruction is to convert a pc. There is no way
524 // to allocate or create instances of class Instr. 539 // to allocate or create instances of class Instr.
525 // Use the At(pc) function to create references to Instr. 540 // Use the At(pc) function to create references to Instr.
526 static Instr* At(uword pc) { return reinterpret_cast<Instr*>(pc); } 541 static Instr* At(uword pc) { return reinterpret_cast<Instr*>(pc); }
527 542
528 #if defined(DEBUG) 543 #if defined(DEBUG)
529 inline void AssertIsImmInstr(Opcode op, Register rs, Register rt, 544 inline void AssertIsImmInstr(Opcode op, Register rs, Register rt,
530 int32_t imm) { 545 int32_t imm) {
531 ASSERT((OpcodeField() == op) && (RsField() == rs) && (RtField() == rt) && 546 ASSERT((OpcodeField() == op) && (RsField() == rs) && (RtField() == rt) &&
532 (SImmField() == imm)); 547 (SImmField() == imm));
533 } 548 }
534 549
535 inline void AssertIsSpecialInstr(SpecialFunction f, Register rs, Register rt, 550 inline void AssertIsSpecialInstr(SpecialFunction f, Register rs, Register rt,
536 Register rd) { 551 Register rd) {
537 ASSERT((OpcodeField() == SPECIAL) && (FunctionField() == f) && 552 ASSERT((OpcodeField() == SPECIAL) && (FunctionField() == f) &&
538 (RsField() == rs) && (RtField() == rt) && 553 (RsField() == rs) && (RtField() == rt) &&
539 (RdField() == rd)); 554 (RdField() == rd));
540 } 555 }
541 #endif // defined(DEBUG) 556 #endif // defined(DEBUG)
542 557
543 private: 558 private:
544 DISALLOW_ALLOCATION(); 559 DISALLOW_ALLOCATION();
545 DISALLOW_IMPLICIT_CONSTRUCTORS(Instr); 560 DISALLOW_IMPLICIT_CONSTRUCTORS(Instr);
546 }; 561 };
547 562
548 } // namespace dart 563 } // namespace dart
549 564
550 #endif // VM_CONSTANTS_MIPS_H_ 565 #endif // VM_CONSTANTS_MIPS_H_
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