Subzero. ARM32. Combine allocas.

src/IceTargetLoweringARM32.cpp

 //===- subzero/src/IceTargetLoweringARM32.cpp - ARM32 lowering ------------===//
 //
 //                        The Subzero Code Generator
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 ///
 /// \file
@@ skipping 247 matching lines @@
     }
 
     OutArgsSizeBytes = applyStackAlignmentTy(OutArgsSizeBytes, Ty);
     OutArgsSizeBytes += typeWidthInBytesOnStack(Ty);
   }
 
   return applyStackAlignment(OutArgsSizeBytes);
 }
 
 void TargetARM32::findMaxStackOutArgsSize() {
-  // MinNeededOutArgsBytes should be updated if the Target ever creates an
+  // MinNeededOutArgsBytes should be updated if the Target ever creates a
   // high-level InstCall that requires more stack bytes.
   constexpr size_t MinNeededOutArgsBytes = 0;
   MaxOutArgsSizeBytes = MinNeededOutArgsBytes;
   for (CfgNode *Node : Func->getNodes()) {
     Context.init(Node);
     while (!Context.atEnd()) {
       PostIncrLoweringContext PostIncrement(Context);
       Inst *CurInstr = Context.getCur();
       if (auto *Call = llvm::dyn_cast<InstCall>(CurInstr)) {
         SizeT OutArgsSizeBytes = getCallStackArgumentsSizeBytes(Call);
         MaxOutArgsSizeBytes = std::max(MaxOutArgsSizeBytes, OutArgsSizeBytes);
       }
     }
   }
 }
 
 void TargetARM32::translateO2() {
   TimerMarker T(TimerStack::TT_O2, Func);
 
   // TODO(stichnot): share passes with X86?
   // https://code.google.com/p/nativeclient/issues/detail?id=4094
   genTargetHelperCalls();
   findMaxStackOutArgsSize();
 
   // Do not merge Alloca instructions, and lay out the stack.
-  static constexpr bool SortAndCombineAllocas = false;
+  static constexpr bool SortAndCombineAllocas = true;
   Func->processAllocas(SortAndCombineAllocas);
   Func->dump("After Alloca processing");
 
   if (!Ctx->getFlags().getPhiEdgeSplit()) {
     // Lower Phi instructions.
     Func->placePhiLoads();
     if (Func->hasError())
       return;
     Func->placePhiStores();
     if (Func->hasError())
@@ skipping 44 matching lines @@
   // Validate the live range computations. The expensive validation call is
   // deliberately only made when assertions are enabled.
   assert(Func->validateLiveness());
   // The post-codegen dump is done here, after liveness analysis and associated
   // cleanup, to make the dump cleaner and more useful.
   Func->dump("After initial ARM32 codegen");
   Func->getVMetadata()->init(VMK_All);
   regAlloc(RAK_Global);
   if (Func->hasError())
     return;
+
   copyRegAllocFromInfWeightVariable64On32(Func->getVariables());
   Func->dump("After linear scan regalloc");
 
   if (Ctx->getFlags().getPhiEdgeSplit()) {
     Func->advancedPhiLowering();
     Func->dump("After advanced Phi lowering");
   }
 
+  ForbidTemporaryWithoutReg _(this);
+
   // Stack frame mapping.
   Func->genFrame();
   if (Func->hasError())
     return;
   Func->dump("After stack frame mapping");
 
   legalizeStackSlots();
   if (Func->hasError())
     return;
   Func->dump("After legalizeStackSlots");
@@ skipping 15 matching lines @@
 }
 
 void TargetARM32::translateOm1() {
   TimerMarker T(TimerStack::TT_Om1, Func);
 
   // TODO: share passes with X86?
   genTargetHelperCalls();
   findMaxStackOutArgsSize();
 
   // Do not merge Alloca instructions, and lay out the stack.
-  static constexpr bool SortAndCombineAllocas = false;
-  Func->processAllocas(SortAndCombineAllocas);
+  static constexpr bool DontSortAndCombineAllocas = false;
+  Func->processAllocas(DontSortAndCombineAllocas);
   Func->dump("After Alloca processing");
 
   Func->placePhiLoads();
   if (Func->hasError())
     return;
   Func->placePhiStores();
   if (Func->hasError())
     return;
   Func->deletePhis();
   if (Func->hasError())
     return;
   Func->dump("After Phi lowering");
 
   Func->doArgLowering();
 
   Func->genCode();
   if (Func->hasError())
     return;
   Func->dump("After initial ARM32 codegen");
 
   regAlloc(RAK_InfOnly);
   if (Func->hasError())
     return;
+
   copyRegAllocFromInfWeightVariable64On32(Func->getVariables());
   Func->dump("After regalloc of infinite-weight variables");
 
+  ForbidTemporaryWithoutReg _(this);
+
   Func->genFrame();
   if (Func->hasError())
     return;
   Func->dump("After stack frame mapping");
 
   legalizeStackSlots();
   if (Func->hasError())
     return;
   Func->dump("After legalizeStackSlots");
 
@@ skipping 73 matching lines @@
     return;
   Ostream &Str = Ctx->getStrEmit();
   if (Var->hasReg()) {
     Str << getRegName(Var->getRegNum(), Var->getType());
     return;
   }
   if (Var->mustHaveReg()) {
     llvm::report_fatal_error(
         "Infinite-weight Variable has no register assigned");
   }
+  assert(!Var->isRematerializable());
   int32_t Offset = Var->getStackOffset();
   int32_t BaseRegNum = Var->getBaseRegNum();
   if (BaseRegNum == Variable::NoRegister) {
     BaseRegNum = getFrameOrStackReg();
   }
   const Type VarTy = Var->getType();
   Str << "[" << getRegName(BaseRegNum, VarTy);
   if (Offset != 0) {
     Str << ", " << getConstantPrefix() << Offset;
   }
@@ skipping 310 matching lines @@
   // Adds the out args space to the stack, and align SP if necessary.
   if (!NeedsStackAlignment) {
     SpillAreaSizeBytes += MaxOutArgsSizeBytes;
   } else {
     uint32_t StackOffset = PreservedRegsSizeBytes;
     uint32_t StackSize = applyStackAlignment(StackOffset + SpillAreaSizeBytes);
     StackSize = applyStackAlignment(StackSize + MaxOutArgsSizeBytes);
     SpillAreaSizeBytes = StackSize - StackOffset;
   }
 
+  // Combine fixed alloca with SpillAreaSize.
+  SpillAreaSizeBytes += FixedAllocaSizeBytes;
+
   // Generate "sub sp, SpillAreaSizeBytes"
   if (SpillAreaSizeBytes) {
     // Use the scratch register if needed to legalize the immediate.
     Operand *SubAmount = legalize(Ctx->getConstantInt32(SpillAreaSizeBytes),
                                   Legal_Reg | Legal_Flex, getReservedTmpReg());
     Variable *SP = getPhysicalRegister(RegARM32::Reg_sp);
     _sub(SP, SP, SubAmount);
+    if (FixedAllocaAlignBytes > ARM32_STACK_ALIGNMENT_BYTES) {
+      alignRegisterPow2(SP, FixedAllocaAlignBytes);
+    }
   }
+
   Ctx->statsUpdateFrameBytes(SpillAreaSizeBytes);
 
   // Fill in stack offsets for stack args, and copy args into registers for
   // those that were register-allocated. Args are pushed right to left, so
   // Arg[0] is closest to the stack/frame pointer.
   Variable *FramePtr = getPhysicalRegister(getFrameOrStackReg());
   size_t BasicFrameOffset = PreservedRegsSizeBytes;
   if (!UsesFramePointer)
     BasicFrameOffset += SpillAreaSizeBytes;
 
@@ skipping 156 matching lines @@
     _sub(ScratchReg, OrigBaseReg, OffsetVal);
   else
     _add(ScratchReg, OrigBaseReg, OffsetVal);
   return ScratchReg;
 }
 
 OperandARM32Mem *TargetARM32::createMemOperand(Type Ty, int32_t Offset,
                                                Variable *OrigBaseReg,
                                                Variable **NewBaseReg,
                                                int32_t *NewBaseOffset) {
+  assert(!OrigBaseReg->isRematerializable());
   if (isLegalMemOffset(Ty, Offset)) {
     return OperandARM32Mem::create(
         Func, Ty, OrigBaseReg,
         llvm::cast<ConstantInteger32>(Ctx->getConstantInt32(Offset)),
         OperandARM32Mem::Offset);
   }
 
   if (*NewBaseReg == nullptr) {
     *NewBaseReg = newBaseRegister(Offset, OrigBaseReg);
     *NewBaseOffset = Offset;
   }
 
   int32_t OffsetDiff = Offset - *NewBaseOffset;
   if (!isLegalMemOffset(Ty, OffsetDiff)) {
     *NewBaseReg = newBaseRegister(Offset, OrigBaseReg);
     *NewBaseOffset = Offset;
     OffsetDiff = 0;
   }
 
+  assert(!(*NewBaseReg)->isRematerializable());
   return OperandARM32Mem::create(
       Func, Ty, *NewBaseReg,
       llvm::cast<ConstantInteger32>(Ctx->getConstantInt32(OffsetDiff)),
       OperandARM32Mem::Offset);
 }
 
 void TargetARM32::legalizeMov(InstARM32Mov *MovInstr, Variable *OrigBaseReg,
                               Variable **NewBaseReg, int32_t *NewBaseOffset) {
   Variable *Dest = MovInstr->getDest();
   assert(Dest != nullptr);
   Type DestTy = Dest->getType();
   assert(DestTy != IceType_i64);
 
   Operand *Src = MovInstr->getSrc(0);
   Type SrcTy = Src->getType();
   (void)SrcTy;
   assert(SrcTy != IceType_i64);
 
   if (MovInstr->isMultiDest() || MovInstr->isMultiSource())
     return;
 
   bool Legalized = false;
   if (!Dest->hasReg()) {
-    auto *const SrcR = llvm::cast<Variable>(Src);
+    auto *SrcR = llvm::cast<Variable>(Src);
     assert(SrcR->hasReg());
+    assert(!SrcR->isRematerializable());
     const int32_t Offset = Dest->getStackOffset();
     // This is a _mov(Mem(), Variable), i.e., a store.
     _str(SrcR, createMemOperand(DestTy, Offset, OrigBaseReg, NewBaseReg,
                                 NewBaseOffset),
          MovInstr->getPredicate());
     // _str() does not have a Dest, so we add a fake-def(Dest).
     Context.insert(InstFakeDef::create(Func, Dest));
     Legalized = true;
   } else if (auto *Var = llvm::dyn_cast<Variable>(Src)) {
-    if (!Var->hasReg()) {
-      const int32_t Offset = Var->getStackOffset();
-      _ldr(Dest, createMemOperand(DestTy, Offset, OrigBaseReg, NewBaseReg,
-                                  NewBaseOffset),
-           MovInstr->getPredicate());
+    if (Var->isRematerializable()) {
+      // Rematerialization arithmetic.
+      const int32_t ExtraOffset =
+          (static_cast<SizeT>(Var->getRegNum()) == getFrameReg())
+              ? getFrameFixedAllocaOffset()
+              : 0;
+
+      const int32_t Offset = Var->getStackOffset() + ExtraOffset;
+      Operand *OffsetRF = legalize(Ctx->getConstantInt32(Offset),
+                                   Legal_Reg | Legal_Flex, Dest->getRegNum());
+      _add(Dest, Var, OffsetRF);
       Legalized = true;
+    } else {
+      if (!Var->hasReg()) {
+        const int32_t Offset = Var->getStackOffset();
+        _ldr(Dest, createMemOperand(DestTy, Offset, OrigBaseReg, NewBaseReg,
+                                    NewBaseOffset),
+             MovInstr->getPredicate());
+        Legalized = true;
+      }
     }
   }
 
   if (Legalized) {
     if (MovInstr->isDestRedefined()) {
       _set_dest_redefined();
     }
     MovInstr->setDeleted();
   }
 }
@@ skipping 50 matching lines @@
     return Operand;
   if (auto *Var64On32 = llvm::dyn_cast<Variable64On32>(Operand))
     return Var64On32->getLo();
   if (auto *Const = llvm::dyn_cast<ConstantInteger64>(Operand))
     return Ctx->getConstantInt32(static_cast<uint32_t>(Const->getValue()));
   if (auto *Mem = llvm::dyn_cast<OperandARM32Mem>(Operand)) {
     // Conservatively disallow memory operands with side-effects (pre/post
     // increment) in case of duplication.
     assert(Mem->getAddrMode() == OperandARM32Mem::Offset ||
            Mem->getAddrMode() == OperandARM32Mem::NegOffset);
+    Variable *BaseR = legalizeToReg(Mem->getBase());
     if (Mem->isRegReg()) {
-      return OperandARM32Mem::create(Func, IceType_i32, Mem->getBase(),
-                                     Mem->getIndex(), Mem->getShiftOp(),
-                                     Mem->getShiftAmt(), Mem->getAddrMode());
+      Variable *IndexR = legalizeToReg(Mem->getIndex());
+      return OperandARM32Mem::create(Func, IceType_i32, BaseR, IndexR,
+                                     Mem->getShiftOp(), Mem->getShiftAmt(),
+                                     Mem->getAddrMode());
     } else {
-      return OperandARM32Mem::create(Func, IceType_i32, Mem->getBase(),
-                                     Mem->getOffset(), Mem->getAddrMode());
+      return OperandARM32Mem::create(Func, IceType_i32, BaseR, Mem->getOffset(),
+                                     Mem->getAddrMode());
     }
   }
   llvm_unreachable("Unsupported operand type");
   return nullptr;
 }
 
 Operand *TargetARM32::hiOperand(Operand *Operand) {
   assert(Operand->getType() == IceType_i64);
   if (Operand->getType() != IceType_i64)
     return Operand;
@@ skipping 11 matching lines @@
     const Type SplitType = IceType_i32;
     if (Mem->isRegReg()) {
       // We have to make a temp variable T, and add 4 to either Base or Index.
       // The Index may be shifted, so adding 4 can mean something else. Thus,
       // prefer T := Base + 4, and use T as the new Base.
       Variable *Base = Mem->getBase();
       Constant *Four = Ctx->getConstantInt32(4);
       Variable *NewBase = Func->makeVariable(Base->getType());
       lowerArithmetic(InstArithmetic::create(Func, InstArithmetic::Add, NewBase,
                                              Base, Four));
-      return OperandARM32Mem::create(Func, SplitType, NewBase, Mem->getIndex(),
+      Variable *BaseR = legalizeToReg(NewBase);
+      Variable *IndexR = legalizeToReg(Mem->getIndex());
+      return OperandARM32Mem::create(Func, SplitType, BaseR, IndexR,
                                      Mem->getShiftOp(), Mem->getShiftAmt(),
                                      Mem->getAddrMode());
     } else {
       Variable *Base = Mem->getBase();
       ConstantInteger32 *Offset = Mem->getOffset();
       assert(!Utils::WouldOverflowAdd(Offset->getValue(), 4));
       int32_t NextOffsetVal = Offset->getValue() + 4;
       constexpr bool ZeroExt = false;
       if (!OperandARM32Mem::canHoldOffset(SplitType, ZeroExt, NextOffsetVal)) {
         // We have to make a temp variable and add 4 to either Base or Offset.
         // If we add 4 to Offset, this will convert a non-RegReg addressing
         // mode into a RegReg addressing mode. Since NaCl sandboxing disallows
         // RegReg addressing modes, prefer adding to base and replacing
         // instead. Thus we leave the old offset alone.
-        Constant *Four = Ctx->getConstantInt32(4);
+        Constant *_4 = Ctx->getConstantInt32(4);
         Variable *NewBase = Func->makeVariable(Base->getType());
         lowerArithmetic(InstArithmetic::create(Func, InstArithmetic::Add,
-                                               NewBase, Base, Four));
+                                               NewBase, Base, _4));
         Base = NewBase;
       } else {
         Offset =
             llvm::cast<ConstantInteger32>(Ctx->getConstantInt32(NextOffsetVal));
       }
-      return OperandARM32Mem::create(Func, SplitType, Base, Offset,
+      Variable *BaseR = legalizeToReg(Base);
+      return OperandARM32Mem::create(Func, SplitType, BaseR, Offset,
                                      Mem->getAddrMode());
     }
   }
   llvm_unreachable("Unsupported operand type");
   return nullptr;
 }
 
 llvm::SmallBitVector TargetARM32::getRegisterSet(RegSetMask Include,
                                                  RegSetMask Exclude) const {
   llvm::SmallBitVector Registers(RegARM32::Reg_NUM);
@@ skipping 18 matching lines @@
     Registers[RegARM32::val] = false;
 
   REGARM32_TABLE
 
 #undef X
 
   return Registers;
 }
 
 void TargetARM32::lowerAlloca(const InstAlloca *Inst) {
-  UsesFramePointer = true;
   // Conservatively require the stack to be aligned. Some stack adjustment
   // operations implemented below assume that the stack is aligned before the
   // alloca. All the alloca code ensures that the stack alignment is preserved
   // after the alloca. The stack alignment restriction can be relaxed in some
   // cases.
   NeedsStackAlignment = true;
 
-  // TODO(stichnot): minimize the number of adjustments of SP, etc.
-  Variable *SP = getPhysicalRegister(RegARM32::Reg_sp);
-  Variable *Dest = Inst->getDest();
-  uint32_t AlignmentParam = Inst->getAlignInBytes();
   // For default align=0, set it to the real value 1, to avoid any
   // bit-manipulation problems below.
-  AlignmentParam = std::max(AlignmentParam, 1u);
+  const uint32_t AlignmentParam = std::max(1u, Inst->getAlignInBytes());
 
   // LLVM enforces power of 2 alignment.
   assert(llvm::isPowerOf2_32(AlignmentParam));
   assert(llvm::isPowerOf2_32(ARM32_STACK_ALIGNMENT_BYTES));
 
-  uint32_t Alignment = std::max(AlignmentParam, ARM32_STACK_ALIGNMENT_BYTES);
-  if (Alignment > ARM32_STACK_ALIGNMENT_BYTES) {
+  const uint32_t Alignment =
+      std::max(AlignmentParam, ARM32_STACK_ALIGNMENT_BYTES);
+  const bool OverAligned = Alignment > ARM32_STACK_ALIGNMENT_BYTES;
+  const bool OptM1 = Ctx->getFlags().getOptLevel() == Opt_m1;
+  const bool AllocaWithKnownOffset = Inst->getKnownFrameOffset();
+  const bool UseFramePointer =
+      hasFramePointer() || OverAligned || !AllocaWithKnownOffset || OptM1;
+
+  if (UseFramePointer)
+    setHasFramePointer();
+
+  Variable *SP = getPhysicalRegister(RegARM32::Reg_sp);
+  if (OverAligned) {
     alignRegisterPow2(SP, Alignment);
   }
+
+  Variable *Dest = Inst->getDest();
   Operand *TotalSize = Inst->getSizeInBytes();
+
   if (const auto *ConstantTotalSize =
           llvm::dyn_cast<ConstantInteger32>(TotalSize)) {
-    uint32_t Value = ConstantTotalSize->getValue();
-    Value = Utils::applyAlignment(Value, Alignment);
-    Operand *SubAmount = legalize(Ctx->getConstantInt32(Value));
-    _sub(SP, SP, SubAmount);
+    const uint32_t Value =
+        Utils::applyAlignment(ConstantTotalSize->getValue(), Alignment);
+    // Constant size alloca.
+    if (!UseFramePointer) {
+      // If we don't need a Frame Pointer, this alloca has a known offset to the
+      // stack pointer. We don't need adjust the stack pointer, nor assign any
+      // value to Dest, as Dest is rematerializable.
+      assert(Dest->isRematerializable());
+      FixedAllocaSizeBytes += Value;
+      Context.insert(InstFakeDef::create(Func, Dest));
+      return;
+    }
+
+    // If a frame pointer is required, then we need to store the alloca'd result
+    // in Dest.
+    Operand *SubAmountRF =
+        legalize(Ctx->getConstantInt32(Value), Legal_Reg | Legal_Flex);
+    _sub(SP, SP, SubAmountRF);
   } else {
     // Non-constant sizes need to be adjusted to the next highest multiple of
     // the required alignment at runtime.
     TotalSize = legalize(TotalSize, Legal_Reg | Legal_Flex);
     Variable *T = makeReg(IceType_i32);
     _mov(T, TotalSize);
     Operand *AddAmount = legalize(Ctx->getConstantInt32(Alignment - 1));
     _add(T, T, AddAmount);
     alignRegisterPow2(T, Alignment);
     _sub(SP, SP, T);
   }
+
+  // Adds back a few bytes to SP to account for the out args area.
   Variable *T = SP;
   if (MaxOutArgsSizeBytes != 0) {
     T = makeReg(getPointerType());
     Operand *OutArgsSizeRF = legalize(
         Ctx->getConstantInt32(MaxOutArgsSizeBytes), Legal_Reg | Legal_Flex);
     _add(T, SP, OutArgsSizeRF);
   }
+
   _mov(Dest, T);
 }
 
 void TargetARM32::div0Check(Type Ty, Operand *SrcLo, Operand *SrcHi) {
   if (isGuaranteedNonzeroInt(SrcLo) || isGuaranteedNonzeroInt(SrcHi))
     return;
   Variable *SrcLoReg = legalizeToReg(SrcLo);
   switch (Ty) {
   default:
     llvm::report_fatal_error("Unexpected type");
@@ skipping 643 matching lines @@
   case InstArithmetic::Urem:
   case InstArithmetic::Srem:
     llvm::report_fatal_error("Call-helper-involved instruction for i64 type "
                              "should have already been handled before");
     return;
   }
 }
 
 void TargetARM32::lowerArithmetic(const InstArithmetic *Inst) {
   Variable *Dest = Inst->getDest();
+
+  if (Dest->isRematerializable()) {
+    Context.insert(InstFakeDef::create(Func, Dest));
+    return;
+  }
+
   if (Dest->getType() == IceType_i1) {
     lowerInt1Arithmetic(Inst);
     return;
   }
 
   Operand *Src0 = legalizeUndef(Inst->getSrc(0));
   Operand *Src1 = legalizeUndef(Inst->getSrc(1));
   if (Dest->getType() == IceType_i64) {
     lowerInt64Arithmetic(Inst->getOp(), Inst->getDest(), Src0, Src1);
     return;
@@ skipping 143 matching lines @@
     Variable *Src0R = Srcs.src0R(this);
     Operand *Src1RF = Srcs.src1RF(this);
     _eor(T, Src0R, Src1RF);
     _mov(Dest, T);
     return;
   }
   case InstArithmetic::Sub: {
     if (Srcs.hasConstOperand()) {
       // TODO(jpp): lowering Src0R here is wrong -- Src0R it is not guaranteed
       // to be used.
-      Variable *Src0R = Srcs.src0R(this);
       if (Srcs.immediateIsFlexEncodable()) {
+        Variable *Src0R = Srcs.src0R(this);
         Operand *Src1RF = Srcs.src1RF(this);
         if (Srcs.swappedOperands()) {
           _rsb(T, Src0R, Src1RF);
         } else {
           _sub(T, Src0R, Src1RF);
         }
         _mov(Dest, T);
         return;
       }
       if (!Srcs.swappedOperands() && Srcs.negatedImmediateIsFlexEncodable()) {
+        Variable *Src0R = Srcs.src0R(this);
         Operand *Src1F = Srcs.negatedSrc1F(this);
         _add(T, Src0R, Src1F);
         _mov(Dest, T);
         return;
       }
     }
     Variable *Src0R = Srcs.unswappedSrc0R(this);
     Variable *Src1R = Srcs.unswappedSrc1R(this);
     _sub(T, Src0R, Src1R);
     _mov(Dest, T);
@@ skipping 44 matching lines @@
   case InstArithmetic::Fdiv:
   case InstArithmetic::Frem:
     llvm::report_fatal_error(
         "Floating point arith should have been handled earlier.");
     return;
   }
 }
 
 void TargetARM32::lowerAssign(const InstAssign *Inst) {
   Variable *Dest = Inst->getDest();
+
+  if (Dest->isRematerializable()) {
+    Context.insert(InstFakeDef::create(Func, Dest));
+    return;
+  }
+
   Operand *Src0 = Inst->getSrc(0);
   assert(Dest->getType() == Src0->getType());
   if (Dest->getType() == IceType_i64) {
     Src0 = legalizeUndef(Src0);
 
     Variable *T_Lo = makeReg(IceType_i32);
     auto *DestLo = llvm::cast<Variable>(loOperand(Dest));
     Operand *Src0Lo = legalize(loOperand(Src0), Legal_Reg | Legal_Flex);
     _mov(T_Lo, Src0Lo);
     _mov(DestLo, T_Lo);
@@ skipping 2190 matching lines @@
       OffsetImm = 0;
     }
   }
 
   assert(BaseVar != nullptr);
   assert(OffsetImm == 0 || OffsetReg == nullptr);
   assert(OffsetReg == nullptr || CanHaveIndex);
   assert(OffsetImm < 0 ? (ValidImmMask & -OffsetImm) == -OffsetImm
                        : (ValidImmMask & OffsetImm) == OffsetImm);
 
+  Variable *BaseR = makeReg(getPointerType());
+  Context.insert(InstAssign::create(Func, BaseR, BaseVar));
   if (OffsetReg != nullptr) {
-    return OperandARM32Mem::create(Func, Ty, BaseVar, OffsetReg, ShiftKind,
+    Variable *OffsetR = makeReg(getPointerType());
+    Context.insert(InstAssign::create(Func, OffsetR, OffsetReg));
+    return OperandARM32Mem::create(Func, Ty, BaseR, OffsetR, ShiftKind,
                                    OffsetRegShamt);
   }
 
   return OperandARM32Mem::create(
-      Func, Ty, BaseVar,
+      Func, Ty, BaseR,
       llvm::cast<ConstantInteger32>(Ctx->getConstantInt32(OffsetImm)));
 }
 
 void TargetARM32::doAddressOptLoad() {
   Inst *Instr = Context.getCur();
   assert(llvm::isa<InstLoad>(Instr));
   Variable *Dest = Instr->getDest();
   Operand *Addr = Instr->getSrc(0);
   if (OperandARM32Mem *Mem =
           formAddressingMode(Dest->getType(), Func, Instr, Addr)) {
@@ skipping 178 matching lines @@
   Type Ty = From->getType();
   // Assert that a physical register is allowed. To date, all calls to
   // legalize() allow a physical register. Legal_Flex converts registers to the
   // right type OperandARM32FlexReg as needed.
   assert(Allowed & Legal_Reg);
 
   // Copied ipsis literis from TargetX86Base<Machine>.
   if (RegNum == Variable::NoRegister) {
     if (Variable *Subst = getContext().availabilityGet(From)) {
       // At this point we know there is a potential substitution available.
-      if (Subst->mustHaveReg() && !Subst->hasReg()) {
+      if (!Subst->isRematerializable() && Subst->mustHaveReg() &&
+          !Subst->hasReg()) {
         // At this point we know the substitution will have a register.
         if (From->getType() == Subst->getType()) {
           // At this point we know the substitution's register is compatible.
           return Subst;
         }
       }
     }
   }
 
   // Go through the various types of operands: OperandARM32Mem,
@@ skipping 137 matching lines @@
       Constant *Offset = Ctx->getConstantSym(0, StrBuf.str(), true);
       Variable *BaseReg = makeReg(getPointerType());
       _movw(BaseReg, Offset);
       _movt(BaseReg, Offset);
       From = formMemoryOperand(BaseReg, Ty);
       return copyToReg(From, RegNum);
     }
   }
 
   if (auto *Var = llvm::dyn_cast<Variable>(From)) {
+    if (Var->isRematerializable()) {
+      // TODO(jpp): We don't need to rematerialize Var if legalize() was invoked
+      // for a Variable in a Mem operand.
+      Variable *T = makeReg(Var->getType(), RegNum);
+      _mov(T, Var);
+      return T;
+    }
     // Check if the variable is guaranteed a physical register. This can happen
     // either when the variable is pre-colored or when it is assigned infinite
     // weight.
     bool MustHaveRegister = (Var->hasReg() || Var->mustHaveReg());
     // We need a new physical register for the operand if:
     //   Mem is not allowed and Var isn't guaranteed a physical
     //   register, or
     //   RegNum is required and Var->getRegNum() doesn't match.
     if ((!(Allowed & Legal_Mem) && !MustHaveRegister) ||
         (RegNum != Variable::NoRegister && RegNum != Var->getRegNum())) {
@@ skipping 36 matching lines @@
   OperandARM32Mem *Mem = llvm::dyn_cast<OperandARM32Mem>(Operand);
   // It may be the case that address mode optimization already creates an
   // OperandARM32Mem, so in that case it wouldn't need another level of
   // transformation.
   if (Mem) {
     return llvm::cast<OperandARM32Mem>(legalize(Mem));
   }
   // If we didn't do address mode optimization, then we only have a
   // base/offset to work with. ARM always requires a base register, so
   // just use that to hold the operand.
-  Variable *Base = legalizeToReg(Operand);
+  Variable *BaseR = legalizeToReg(Operand);
   return OperandARM32Mem::create(
-      Func, Ty, Base,
+      Func, Ty, BaseR,
       llvm::cast<ConstantInteger32>(Ctx->getConstantZero(IceType_i32)));
 }
 
 Variable64On32 *TargetARM32::makeI64RegPair() {
   Variable64On32 *Reg =
       llvm::cast<Variable64On32>(Func->makeVariable(IceType_i64));
   Reg->setMustHaveReg();
   Reg->initHiLo(Func);
   Reg->getLo()->setMustNotHaveReg();
   Reg->getHi()->setMustNotHaveReg();
   return Reg;
 }
 
 Variable *TargetARM32::makeReg(Type Type, int32_t RegNum) {
   // There aren't any 64-bit integer registers for ARM32.
   assert(Type != IceType_i64);
+  assert(AllowTemporaryWithNoReg || RegNum != Variable::NoRegister);
   Variable *Reg = Func->makeVariable(Type);
   if (RegNum == Variable::NoRegister)
     Reg->setMustHaveReg();
   else
     Reg->setRegNum(RegNum);
   return Reg;
 }
 
-void TargetARM32::alignRegisterPow2(Variable *Reg, uint32_t Align) {
+void TargetARM32::alignRegisterPow2(Variable *Reg, uint32_t Align,
+                                    int32_t TmpRegNum) {
   assert(llvm::isPowerOf2_32(Align));
   uint32_t RotateAmt;
   uint32_t Immed_8;
   Operand *Mask;
   // Use AND or BIC to mask off the bits, depending on which immediate fits (if
   // it fits at all). Assume Align is usually small, in which case BIC works
   // better. Thus, this rounds down to the alignment.
   if (OperandARM32FlexImm::canHoldImm(Align - 1, &RotateAmt, &Immed_8)) {
-    Mask = legalize(Ctx->getConstantInt32(Align - 1), Legal_Reg | Legal_Flex);
+    Mask = legalize(Ctx->getConstantInt32(Align - 1), Legal_Reg | Legal_Flex,
+                    TmpRegNum);
     _bic(Reg, Reg, Mask);
   } else {
-    Mask = legalize(Ctx->getConstantInt32(-Align), Legal_Reg | Legal_Flex);
+    Mask = legalize(Ctx->getConstantInt32(-Align), Legal_Reg | Legal_Flex,
+                    TmpRegNum);
     _and(Reg, Reg, Mask);
   }
 }
 
 void TargetARM32::postLower() {
   if (Ctx->getFlags().getOptLevel() == Opt_m1)
     return;
   markRedefinitions();
   Context.availabilityUpdate();
 }
@@ skipping 515 matching lines @@
   // Technically R9 is used for TLS with Sandboxing, and we reserve it.
   // However, for compatibility with current NaCl LLVM, don't claim that.
   Str << ".eabi_attribute 14, 3   @ Tag_ABI_PCS_R9_use: Not used\n";
 }
 
 llvm::SmallBitVector TargetARM32::TypeToRegisterSet[IceType_NUM];
 llvm::SmallBitVector TargetARM32::RegisterAliases[RegARM32::Reg_NUM];
 llvm::SmallBitVector TargetARM32::ScratchRegs;
 
 } // end of namespace Ice