Insert denominator zero checks for NaCl

lib/Target/ARM/ARMTargetMachine.cpp

 //===-- ARMTargetMachine.cpp - Define TargetMachine for ARM ---------------===//
 //
 //                     The LLVM Compiler Infrastructure
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 //
 //
 //===----------------------------------------------------------------------===//
 
 #include "ARMTargetMachine.h"
 #include "ARM.h"
 #include "ARMFrameLowering.h"
 #include "llvm/CodeGen/Passes.h"
 #include "llvm/MC/MCAsmInfo.h"
 #include "llvm/PassManager.h"
 #include "llvm/Support/CommandLine.h"
 #include "llvm/Support/FormattedStream.h"
 #include "llvm/Support/TargetRegistry.h"
 #include "llvm/Target/TargetOptions.h"
+// @LOCALMOD-START
+#include "llvm/Transforms/NaCl.h"
+// @LOCALMOD-END
 #include "llvm/Transforms/Scalar.h"
 using namespace llvm;
 
 static cl::opt<bool>
 EnableGlobalMerge("global-merge", cl::Hidden,
                   cl::desc("Enable global merge pass"),
                   cl::init(true));
 
 // @LOCALMOD-START
 namespace llvm {
@@ skipping 101 matching lines @@
 
   const ARMSubtarget &getARMSubtarget() const {
     return *getARMTargetMachine().getSubtargetImpl();
   }
 
   virtual bool addPreISel();
   virtual bool addInstSelector();
   virtual bool addPreRegAlloc();
   virtual bool addPreSched2();
   virtual bool addPreEmitPass();
+// @LOCALMOD-START
+  virtual void addIRPasses();
+// @LOCALMOD-END
 };
 } // namespace
 
 TargetPassConfig *ARMBaseTargetMachine::createPassConfig(PassManagerBase &PM) {
   return new ARMPassConfig(this, PM);
 }
 
 bool ARMPassConfig::addPreISel() {
   if (TM->getOptLevel() != CodeGenOpt::None && EnableGlobalMerge)
     addPass(createGlobalMergePass(TM->getTargetLowering()));
@@ skipping 68 matching lines @@
   // @LOCALMOD-START
   // This pass does all the heavy sfi lifting.
   if (getARMSubtarget().isTargetNaCl()) {
     addPass(createARMNaClRewritePass());
   }
   // @LOCALMOD-END
  
   return true;
 }
 
+// @LOCALMOD-START
+void ARMPassConfig::addIRPasses() {
+  if (getARMSubtarget().isTargetNaCl()) {
+    addPass(createInsertDivideCheckPass());
+  }
+  TargetPassConfig::addIRPasses();
+}
+// @LOCALMOD-END
+
 bool ARMBaseTargetMachine::addCodeEmitter(PassManagerBase &PM,
                                           JITCodeEmitter &JCE) {
   // Machine code emitter pass for ARM.
   PM.add(createARMJITCodeEmitterPass(*this, JCE));
   return false;
 }