Add MVN (register, immediate) to ARM integrated assembler.

src/IceAssemblerARM32.cpp

 //===- subzero/src/IceAssemblerARM32.cpp - Assembler for ARM32 --*- C++ -*-===//
 //
 // Copyright (c) 2013, the Dart project authors.  Please see the AUTHORS file
 // for details. All rights reserved. Use of this source code is governed by a
 // BSD-style license that can be found in the LICENSE file.
 //
 // Modified by the Subzero authors.
 //
 //===----------------------------------------------------------------------===//
 //
@@ skipping 169 matching lines @@
 // The way an operand was decoded in functions decodeOperand and decodeAddress
 // below.
 enum DecodedResult {
   // Unable to decode, value left undefined.
   CantDecode = 0,
   // Value is register found.
   DecodedAsRegister,
   // Value=rrrriiiiiiii where rrrr is the rotation, and iiiiiiii is the imm8
   // value.
   DecodedAsRotatedImm8,
-  // i.e. 0000000pu0w0nnnn0000iiiiiiiiiiii where nnnn is the base register Rn,
+  // Value=0000000pu0w0nnnn0000iiiiiiiiiiii where nnnn is the base register Rn,
   // p=1 if pre-indexed addressing, u=1 if offset positive, w=1 if writeback to
   // Rn should be used, and iiiiiiiiiiii defines the rotated Imm8 value.
   DecodedAsImmRegOffset,
-  // i.e. 0000000pu0w00nnnnttttiiiiiss0mmmm where nnnn is the base register Rn,
+  // Value=0000000pu0w00nnnnttttiiiiiss0mmmm where nnnn is the base register Rn,
   // mmmm is the index register Rm, iiiii is the shift amount, ss is the shift
   // kind, p=1 if pre-indexed addressing, u=1 if offset positive, and w=1 if
   // writeback to Rn.
   DecodedAsShiftRotateImm5,
-  // i.e. 000000000000000000000iiiii0000000 iiii defines Imm5 value to shift.
+  // Value=000000000000000000000iiiii0000000 iiii defines the Imm5 value to
+  // shift.
   DecodedAsShiftImm5,
   // Value is 32bit integer constant.
   DecodedAsConstI32
 };
 
 // Sets Encoding to a rotated Imm8 encoding of Value, if possible.
 inline IValueT encodeRotatedImm8(IValueT RotateAmt, IValueT Immed8) {
   assert(RotateAmt < (1 << kRotateBits));
   assert(Immed8 < (1 << kImmed8Bits));
   return (RotateAmt << kRotateShift) | (Immed8 << kImmed8Shift);
 }
 
 // Encodes iiiiitt0mmmm for data-processing (2nd) operands where iiiii=Imm5,
 // tt=Shift, and mmmm=Rm.
 IValueT encodeShiftRotateImm5(IValueT Rm, OperandARM32::ShiftKind Shift,
                               IOffsetT imm5) {
   (void)kShiftImmBits;
   assert(imm5 < (1 << kShiftImmBits));
   return (imm5 << kShiftImmShift) | (encodeShift(Shift) << kShiftShift) | Rm;
 }
 
-// Encodes mmmmtt01ssss for data-processing (2nd) operands where mmmm=Rm,
-// ssss=Rs, and tt=Shift.
+// Encodes mmmmtt01ssss for data-processing operands where mmmm=Rm, ssss=Rs, and
+// tt=Shift.
 IValueT encodeShiftRotateReg(IValueT Rm, OperandARM32::ShiftKind Shift,
                              IValueT Rs) {
   return (Rs << kRsShift) | (encodeShift(Shift) << kShiftShift) | B4 |
          (Rm << kRmShift);
 }
 
 DecodedResult decodeOperand(const Operand *Opnd, IValueT &Value) {
   if (const auto *Var = llvm::dyn_cast<Variable>(Opnd)) {
     if (Var->hasReg()) {
       Value = Var->getRegNum();
@@ skipping 241 matching lines @@
     return setNeedsTextFixup();
   IValueT Rn;
   if (decodeOperand(OpRn, Rn) != DecodedAsRegister)
     return setNeedsTextFixup();
   emitType01(Opcode, Rd, Rn, OpSrc1, SetFlags, Cond, RuleChecks);
 }
 
 void AssemblerARM32::emitType01(IValueT Opcode, IValueT Rd, IValueT Rn,
                                 const Operand *OpSrc1, bool SetFlags,
                                 CondARM32::Cond Cond, EmitChecks RuleChecks) {
-  switch (RuleChecks) {
-  case NoChecks:
-    break;
-  case RdIsPcAndSetFlags:
-    if (((Rd == RegARM32::Encoded_Reg_pc) && SetFlags))
-      // Conditions of rule violated.
-      return setNeedsTextFixup();
-    break;
-  }
 
   IValueT Src1Value;
   // TODO(kschimpf) Other possible decodings of data operations.
   switch (decodeOperand(OpSrc1, Src1Value)) {
   default:
     return setNeedsTextFixup();
   case DecodedAsRegister: {
     // XXX (register)
     //   xxx{s}<c> <Rd>, <Rn>, <Rm>{, <shiff>}
     //
@@ skipping 54 matching lines @@
   if (!needsTextFixup())
     L->linkTo(Position);
 }
 
 void AssemblerARM32::emitCompareOp(IValueT Opcode, const Operand *OpRn,
                                    const Operand *OpSrc1,
                                    CondARM32::Cond Cond) {
   // XXX (register)
   //   XXX<c> <Rn>, <Rm>{, <shift>}
   //
-  // ccccyyyxxxx1nnnn0000iiiiitt0mmmm where cccc=Cond, nnnn=Rn, mmmm=Rm,
-  // iiiii=Shift, tt=ShiftKind, yyy=kInstTypeDataRegister, and xxxx=Opcode.
+  // ccccyyyxxxx1nnnn0000iiiiitt0mmmm where cccc=Cond, nnnn=Rn, mmmm=Rm, iiiii
+  // defines shift constant, tt=ShiftKind, yyy=kInstTypeDataRegister, and
+  // xxxx=Opcode.
   //
   // XXX (immediate)
   //  XXX<c> <Rn>, #<RotatedImm8>
   //
   // ccccyyyxxxx1nnnn0000iiiiiiiiiiii where cccc=Cond, dddd=Rd, nnnn=Rn,
   // yyy=kInstTypeDataImmdiate, xxxx=Opcode, and iiiiiiiiiiii=Src1Value
   // defining RotatedImm8.
   constexpr bool SetFlags = true;
   constexpr IValueT Rd = RegARM32::Encoded_Reg_r0;
   IValueT Rn;
@@ skipping 461 matching lines @@
   // install the correct bits.
   constexpr bool IsMovW = false;
   emitFixup(createMoveFixup(IsMovW, Src));
   constexpr IValueT Imm16 = 0;
   const IValueT Encoding = encodeCondition(Cond) << kConditionShift | B25 |
                            B24 | B22 | ((Imm16 >> 12) << 16) | Rd << kRdShift |
                            (Imm16 & 0xfff);
   emitInst(Encoding);
 }
 
+void AssemblerARM32::mvn(const Operand *OpRd, const Operand *OpSrc,
+                         CondARM32::Cond Cond) {
+  // MVN (immediate) - ARM section A8.8.115, encoding A1:
+  //   mvn{s}<c> <Rd>, #<const>
+  //
+  // cccc0011111s0000ddddiiiiiiiiiiii where cccc=Cond, s=SetFlags=0, dddd=Rd,
+  // and iiiiiiiiiiii=const
+  //
+  // MVN (register) - ARM section A8.8.116, encoding A1:
+  //   mvn{s}<c> <Rd>, <Rm>{, <shift>
+  //
+  // cccc0001111s0000ddddiiiiitt0mmmm where cccc=Cond, s=SetFlags=0, dddd=Rd,
+  // mmmm=Rm, iiii defines shift constant, and tt=ShiftKind.
+  IValueT Rd;
+  if (decodeOperand(OpRd, Rd) != DecodedAsRegister)
+    return setNeedsTextFixup();
+  constexpr IValueT MvnOpcode = B3 | B2 | B1 | B0; // i.e. 1111
+  constexpr IValueT Rn = 0;
+  constexpr bool SetFlags = false;
+  emitType01(MvnOpcode, Rd, Rn, OpSrc, SetFlags, Cond, RdIsPcAndSetFlags);
+}
+
 void AssemblerARM32::sbc(const Operand *OpRd, const Operand *OpRn,
                          const Operand *OpSrc1, bool SetFlags,
                          CondARM32::Cond Cond) {
   // SBC (register) - ARM section 18.8.162, encoding A1:
   //   sbc{s}<c> <Rd>, <Rn>, <Rm>{, <shift>}
   //
   // cccc0000110snnnnddddiiiiitt0mmmm where cccc=Cond, dddd=Rd, nnnn=Rn,
   // mmmm=Rm, iiiii=Shift, tt=ShiftKind, and s=SetFlags.
   //
   // SBC (Immediate) - ARM section A8.8.161, encoding A1:
@@ skipping 311 matching lines @@
     // rr defined (RotationValue) rotate.
     constexpr IValueT Opcode = B26 | B25 | B23 | B22 | B21 | B20;
     emitUxt(Cond, Opcode, Rd, Rn, Rm, Rotation);
     return;
   }
   }
 }
 
 } // end of namespace ARM32
 } // end of namespace Ice