Add MVN (register, immediate) to ARM integrated assembler.

src/DartARM32/assembler_arm.cc

 // Copyright (c) 2013, the Dart project authors.  Please see the AUTHORS file
 // for details. All rights reserved. Use of this source code is governed by a
 // BSD-style license that can be found in the LICENSE file.
 //
 // This is forked from Dart revision df52deea9f25690eb8b66c5995da92b70f7ac1fe
 // Please update the (git) revision if we merge changes from Dart.
 // https://code.google.com/p/dart/wiki/GettingTheSource
 
 #include "vm/globals.h"  // NOLINT
 #if defined(TARGET_ARCH_ARM)
@@ skipping 74 matching lines @@
   int32_t encoding = static_cast<int32_t>(cond) << kConditionShift |
                      type << kTypeShift |
                      static_cast<int32_t>(opcode) << kOpcodeShift |
                      set_cc << kSShift |
                      static_cast<int32_t>(rn) << kRnShift |
                      static_cast<int32_t>(rd) << kRdShift |
                      o.encoding();
   Emit(encoding);
 }
 
-// Moved to ARM32::AssemblerARM32::emitType05.
+// Moved to ARM32::AssemblerARM32::emitType05()
 void Assembler::EmitType5(Condition cond, int32_t offset, bool link) {
   ASSERT(cond != kNoCondition);
   int32_t encoding = static_cast<int32_t>(cond) << kConditionShift |
                      5 << kTypeShift |
                      (link ? 1 : 0) << kLinkShift;
   Emit(Assembler::EncodeBranchOffset(offset, encoding));
 }
 
 // Moved to ARM32::AssemblerARM32::emitMemOp()
 void Assembler::EmitMemOp(Condition cond,
@@ skipping 191 matching lines @@
   EmitType01(cond, o.type(), MOV, 0, R0, rd, o);
 }
 #endif
 
 void Assembler::movs(Register rd, Operand o, Condition cond) {
   EmitType01(cond, o.type(), MOV, 1, R0, rd, o);
 }
 
 
 #if 0
-// Moved to ARM32::AssemblerARM32::bic();
+// Moved to ARM32::AssemblerARM32::bic()
 void Assembler::bic(Register rd, Register rn, Operand o, Condition cond) {
   EmitType01(cond, o.type(), BIC, 0, rn, rd, o);
 }
 
-// Moved to ARM32::AssemblerARM32::bic();
+// Moved to ARM32::AssemblerARM32::bic()
 void Assembler::bics(Register rd, Register rn, Operand o, Condition cond) {
   EmitType01(cond, o.type(), BIC, 1, rn, rd, o);
 }
-#endif
 
+// Moved to ARM32::AssemblerARM32::mvn()
 void Assembler::mvn(Register rd, Operand o, Condition cond) {
   EmitType01(cond, o.type(), MVN, 0, R0, rd, o);
 }
 
-
+// Moved to ARM32::AssemblerARM32::mvn()
 void Assembler::mvns(Register rd, Operand o, Condition cond) {
   EmitType01(cond, o.type(), MVN, 1, R0, rd, o);
 }
-
+#endif
 
 void Assembler::clz(Register rd, Register rm, Condition cond) {
   ASSERT(rd != kNoRegister);
   ASSERT(rm != kNoRegister);
   ASSERT(cond != kNoCondition);
   ASSERT(rd != PC);
   ASSERT(rm != PC);
   int32_t encoding = (static_cast<int32_t>(cond) << kConditionShift) |
                      B24 | B22 | B21 | (0xf << 16) |
                      (static_cast<int32_t>(rd) << kRdShift) |
                      (0xf << 8) | B4 | static_cast<int32_t>(rm);
   Emit(encoding);
 }
 
 
 #if
-// Moved to ARM32::AssemblerARM32::movw
+// Moved to ARM32::AssemblerARM32::movw()
 void Assembler::movw(Register rd, uint16_t imm16, Condition cond) {
   ASSERT(cond != kNoCondition);
   int32_t encoding = static_cast<int32_t>(cond) << kConditionShift |
                      B25 | B24 | ((imm16 >> 12) << 16) |
                      static_cast<int32_t>(rd) << kRdShift | (imm16 & 0xfff);
   Emit(encoding);
 }
 
 
-// Moved to ARM32::AssemblerARM32::movt
+// Moved to ARM32::AssemblerARM32::movt()
 void Assembler::movt(Register rd, uint16_t imm16, Condition cond) {
   ASSERT(cond != kNoCondition);
   int32_t encoding = static_cast<int32_t>(cond) << kConditionShift |
                      B25 | B24 | B22 | ((imm16 >> 12) << 16) |
                      static_cast<int32_t>(rd) << kRdShift | (imm16 & 0xfff);
   Emit(encoding);
 }
 #endif
 
 #if 0
-// Moved to ARM32::AssemblerARM32::emitMulOp
+// Moved to ARM32::AssemblerARM32::emitMulOp()
 void Assembler::EmitMulOp(Condition cond, int32_t opcode,
                           Register rd, Register rn,
                           Register rm, Register rs) {
   ASSERT(rd != kNoRegister);
   ASSERT(rn != kNoRegister);
   ASSERT(rm != kNoRegister);
   ASSERT(rs != kNoRegister);
   ASSERT(cond != kNoCondition);
   int32_t encoding = opcode |
       (static_cast<int32_t>(cond) << kConditionShift) |
       (static_cast<int32_t>(rn) << kRnShift) |
       (static_cast<int32_t>(rd) << kRdShift) |
       (static_cast<int32_t>(rs) << kRsShift) |
       B7 | B4 |
       (static_cast<int32_t>(rm) << kRmShift);
   Emit(encoding);
 }
 
-// Moved to ARM32::AssemblerARM32::mul
+// Moved to ARM32::AssemblerARM32::mul()
 void Assembler::mul(Register rd, Register rn, Register rm, Condition cond) {
   // Assembler registers rd, rn, rm are encoded as rn, rm, rs.
   EmitMulOp(cond, 0, R0, rd, rn, rm);
 }
 #endif
 
 // Like mul, but sets condition flags.
 void Assembler::muls(Register rd, Register rn, Register rm, Condition cond) {
   EmitMulOp(cond, B20, R0, rd, rn, rm);
 }
@@ skipping 1703 matching lines @@
   ASSERT(ICData::IsValidRangeFeedbackIndex(index));
   ComputeRange(scratch1, value, scratch2, miss);
   ldr(scratch2, FieldAddress(ic_data, ICData::state_bits_offset()));
   orr(scratch2,
       scratch2,
       Operand(scratch1, LSL, ICData::RangeFeedbackShift(index)));
   str(scratch2, FieldAddress(ic_data, ICData::state_bits_offset()));
 }
 
 #if 0
-// Moved to ::canEncodeBranchoffset in IceAssemblerARM32.cpp.
+// Moved to ::canEncodeBranchoffset() in IceAssemblerARM32.cpp.
 static bool CanEncodeBranchOffset(int32_t offset) {
   ASSERT(Utils::IsAligned(offset, 4));
   // Note: This check doesn't take advantage of the fact that offset>>2
   // is stored (allowing two more bits in address space).
   return Utils::IsInt(Utils::CountOneBits(kBranchOffsetMask), offset);
 }
 
-// Moved to ARM32::AssemblerARM32::encodeBranchOffset.
+// Moved to ARM32::AssemblerARM32::encodeBranchOffset()
 int32_t Assembler::EncodeBranchOffset(int32_t offset, int32_t inst) {
   // The offset is off by 8 due to the way the ARM CPUs read PC.
   offset -= Instr::kPCReadOffset;
 
   if (!CanEncodeBranchOffset(offset)) {
     ASSERT(!use_far_branches());
     Thread::Current()->long_jump_base()->Jump(
         1, Object::branch_offset_error());
   }
 
   // Properly preserve only the bits supported in the instruction.
   offset >>= 2;
   offset &= kBranchOffsetMask;
   return (inst & ~kBranchOffsetMask) | offset;
 }
 
-// Moved to AssemberARM32::decodeBranchOffset.
+// Moved to AssemberARM32::decodeBranchOffset()
 int Assembler::DecodeBranchOffset(int32_t inst) {
   // Sign-extend, left-shift by 2, then add 8.
   return ((((inst & kBranchOffsetMask) << 8) >> 6) + Instr::kPCReadOffset);
 }
 #endif
 
 static int32_t DecodeARMv7LoadImmediate(int32_t movt, int32_t movw) {
   int32_t offset = 0;
   offset |= (movt & 0xf0000) << 12;
   offset |= (movt & 0xfff) << 16;
@@ skipping 1550 matching lines @@
 
 
 const char* Assembler::FpuRegisterName(FpuRegister reg) {
   ASSERT((0 <= reg) && (reg < kNumberOfFpuRegisters));
   return fpu_reg_names[reg];
 }
 
 }  // namespace dart
 
 #endif  // defined TARGET_ARCH_ARM