PPC: [turbofan] Implemented the TruncateFloat64ToUint64 TurboFan operator.

src/ppc/constants-ppc.h

 // Copyright 2014 the V8 project authors. All rights reserved.
 // Use of this source code is governed by a BSD-style license that can be
 // found in the LICENSE file.
 
 #ifndef V8_PPC_CONSTANTS_PPC_H_
 #define V8_PPC_CONSTANTS_PPC_H_
 
 #include <stdint.h>
 
 #include "src/base/logging.h"
@@ skipping 257 matching lines @@
   FDIV = 18 << 1,   // Floating Divide
   FSUB = 20 << 1,   // Floating Subtract
   FADD = 21 << 1,   // Floating Add
   FSQRT = 22 << 1,  // Floating Square Root
   FSEL = 23 << 1,   // Floating Select
   FMUL = 25 << 1,   // Floating Multiply
   FMSUB = 28 << 1,  // Floating Multiply-Subtract
   FMADD = 29 << 1,  // Floating Multiply-Add
 
   // Bits 10-1
-  FCMPU = 0 << 1,     // Floating Compare Unordered
-  FRSP = 12 << 1,     // Floating-Point Rounding
-  FCTIW = 14 << 1,    // Floating Convert to Integer Word X-form
-  FCTIWZ = 15 << 1,   // Floating Convert to Integer Word with Round to Zero
-  FNEG = 40 << 1,     // Floating Negate
-  MCRFS = 64 << 1,    // Move to Condition Register from FPSCR
-  FMR = 72 << 1,      // Floating Move Register
-  MTFSFI = 134 << 1,  // Move to FPSCR Field Immediate
-  FABS = 264 << 1,    // Floating Absolute Value
-  FRIN = 392 << 1,    // Floating Round to Integer Nearest
-  FRIZ = 424 << 1,    // Floating Round to Integer Toward Zero
-  FRIP = 456 << 1,    // Floating Round to Integer Plus
-  FRIM = 488 << 1,    // Floating Round to Integer Minus
-  MFFS = 583 << 1,    // move from FPSCR x-form
-  MTFSF = 711 << 1,   // move to FPSCR fields XFL-form
-  FCFID = 846 << 1,   // Floating convert from integer doubleword
-  FCTID = 814 << 1,   // Floating convert from integer doubleword
-  FCTIDZ = 815 << 1,  // Floating convert from integer doubleword
-  FCFIDU = 974 << 1   // Floating convert from integer doubleword unsigned
+  FCMPU = 0 << 1,      // Floating Compare Unordered
+  FRSP = 12 << 1,      // Floating-Point Rounding
+  FCTIW = 14 << 1,     // Floating Convert to Integer Word X-form
+  FCTIWZ = 15 << 1,    // Floating Convert to Integer Word with Round to Zero
+  FNEG = 40 << 1,      // Floating Negate
+  MCRFS = 64 << 1,     // Move to Condition Register from FPSCR
+  FMR = 72 << 1,       // Floating Move Register
+  MTFSFI = 134 << 1,   // Move to FPSCR Field Immediate
+  FABS = 264 << 1,     // Floating Absolute Value
+  FRIN = 392 << 1,     // Floating Round to Integer Nearest
+  FRIZ = 424 << 1,     // Floating Round to Integer Toward Zero
+  FRIP = 456 << 1,     // Floating Round to Integer Plus
+  FRIM = 488 << 1,     // Floating Round to Integer Minus
+  MFFS = 583 << 1,     // move from FPSCR x-form
+  MTFSF = 711 << 1,    // move to FPSCR fields XFL-form
+  FCTID = 814 << 1,    // Floating convert to integer doubleword
+  FCTIDZ = 815 << 1,   // ^^^ with round toward zero
+  FCFID = 846 << 1,    // Floating convert from integer doubleword
+  FCTIDU = 942 << 1,   // Floating convert to integer doubleword unsigned
+  FCTIDUZ = 943 << 1,  // ^^^ with round toward zero
+  FCFIDU = 974 << 1    // Floating convert from integer doubleword unsigned
 };
 
 enum OpcodeExt5 {
   // Bits 4-2
   RLDICL = 0 << 1,  // Rotate Left Double Word Immediate then Clear Left
   RLDICR = 2 << 1,  // Rotate Left Double Word Immediate then Clear Right
   RLDIC = 4 << 1,   // Rotate Left Double Word Immediate then Clear
   RLDIMI = 6 << 1,  // Rotate Left Double Word Immediate then Mask Insert
   // Bits 4-1
   RLDCL = 8 << 1,  // Rotate Left Double Word then Clear Left
@@ skipping 272 matching lines @@
   // Lookup the register number for the name provided.
   static int Number(const char* name);
 
  private:
   static const char* names_[kNumDoubleRegisters];
 };
 }  // namespace internal
 }  // namespace v8
 
 #endif  // V8_PPC_CONSTANTS_PPC_H_