Add recognizing register-shifted forms in ARM assembler.

src/IceAssemblerARM32.cpp

Index: src/IceAssemblerARM32.cpp
diff --git a/src/IceAssemblerARM32.cpp b/src/IceAssemblerARM32.cpp
index cd4735b02d84139512bc2f93f3cef4a1ea68917b..29fcd027eb22e89466bb6254240a3db787fa23c6 100644
--- a/src/IceAssemblerARM32.cpp
+++ b/src/IceAssemblerARM32.cpp
@@ -199,6 +199,9 @@ enum DecodedResult {
   // Value=000000000000000000000iiiii0000000 iiii defines the Imm5 value to
   // shift.
   DecodedAsShiftImm5,
+  // i.e. iiiiiss0mmmm where mmmm is the register to rotate, ss is the shift
+  // kind, and iiiii is the shift amount.
+  DecodedAsShiftedRegister,
   // Value is 32bit integer constant.
   DecodedAsConstI32
 };
@@ -228,6 +231,7 @@ IValueT encodeShiftRotateReg(IValueT Rm, OperandARM32::ShiftKind Shift,
 }
 
 DecodedResult decodeOperand(const Operand *Opnd, IValueT &Value) {
+  Value = 0; // Make sure initialized.
   if (const auto *Var = llvm::dyn_cast<Variable>(Opnd)) {
     if (Var->hasReg()) {
       Value = Var->getRegNum();
@@ -247,6 +251,18 @@ DecodedResult decodeOperand(const Operand *Opnd, IValueT &Value) {
     Value = Const->getValue();
     return DecodedAsConstI32;
   }
+  if (const auto *FlexReg = llvm::dyn_cast<OperandARM32FlexReg>(Opnd)) {
+    Operand *Amt = FlexReg->getShiftAmt();
+    if (const auto *Imm5 = llvm::dyn_cast<OperandARM32ShAmtImm>(Amt)) {
+      IValueT Rm;
+      if (decodeOperand(FlexReg->getReg(), Rm) != DecodedAsRegister)
+        return CantDecode;
+      Value =
+          encodeShiftRotateImm5(Rm, FlexReg->getShiftOp(), Imm5->getShAmtImm());
+      return DecodedAsShiftedRegister;
+    }
+    // TODO(kschimpf): Handle case where Amt is a register?
+  }
   if (const auto *ShImm = llvm::dyn_cast<OperandARM32ShAmtImm>(Opnd)) {
     const IValueT Immed5 = ShImm->getShAmtImm();
     assert(Immed5 < (1 << kShiftImmBits));
@@ -271,6 +287,7 @@ IValueT decodeImmRegOffset(RegARM32::GPRRegister Reg, IOffsetT Offset,
 // based on how ARM represents the address. Returns how the value was encoded.
 DecodedResult decodeAddress(const Operand *Opnd, IValueT &Value,
                             const AssemblerARM32::TargetInfo &TInfo) {
+  Value = 0; // Make sure initialized.
   if (const auto *Var = llvm::dyn_cast<Variable>(Opnd)) {
     // Should be a stack variable, with an offset.
     if (Var->hasReg())
@@ -500,6 +517,12 @@ void AssemblerARM32::emitType01(IValueT Opcode, IValueT Rd, IValueT Rn,
                RuleChecks);
     return;
   }
+  case DecodedAsShiftedRegister: {
+    // Form is defined in case DecodedAsRegister. (i.e. XXX (register)).
+    emitType01(Cond, kInstTypeDataRegister, Opcode, SetFlags, Rn, Rd, Src1Value,
+               RuleChecks);
+    return;
+  }
   case DecodedAsConstI32: {
     // See if we can convert this to an XXX (immediate).
     IValueT RotateAmt;