Add LDR/LDRB (register) to ARM integrated assembler.

src/IceInstARM32.h

 //===- subzero/src/IceInstARM32.h - ARM32 machine instructions --*- C++ -*-===//
 //
 //                        The Subzero Code Generator
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 ///
 /// \file
@@ skipping 58 matching lines @@
 class OperandARM32Mem : public OperandARM32 {
   OperandARM32Mem() = delete;
   OperandARM32Mem(const OperandARM32Mem &) = delete;
   OperandARM32Mem &operator=(const OperandARM32Mem &) = delete;
 
 public:
   /// Memory operand addressing mode.
   /// The enum value also carries the encoding.
   // TODO(jvoung): unify with the assembler.
   enum AddrMode {
-    // bit encoding P U W
+    // bit encoding P U 0 W
     Offset = (8 | 4 | 0) << 21,      // offset (w/o writeback to base)
     PreIndex = (8 | 4 | 1) << 21,    // pre-indexed addressing with writeback
     PostIndex = (0 | 4 | 0) << 21,   // post-indexed addressing with writeback
     NegOffset = (8 | 0 | 0) << 21,   // negative offset (w/o writeback to base)
     NegPreIndex = (8 | 0 | 1) << 21, // negative pre-indexed with writeback
     NegPostIndex = (0 | 0 | 0) << 21 // negative post-indexed with writeback
   };
 
   /// Provide two constructors.
   /// NOTE: The Variable-typed operands have to be registers.
@@ skipping 1225 matching lines @@
 // default implementations. Without this, there is the possibility of ODR
 // violations and link errors.
 
 template <> void InstARM32Ldr::emit(const Cfg *Func) const;
 template <> void InstARM32Movw::emit(const Cfg *Func) const;
 template <> void InstARM32Movt::emit(const Cfg *Func) const;
 
 } // end of namespace Ice
 
 #endif // SUBZERO_SRC_ICEINSTARM32_H