Add LDR/LDRB (register) to ARM integrated assembler.

src/IceAssemblerARM32.cpp

 //===- subzero/src/IceAssemblerARM32.cpp - Assembler for ARM32 --*- C++ -*-===//
 //
 // Copyright (c) 2013, the Dart project authors.  Please see the AUTHORS file
 // for details. All rights reserved. Use of this source code is governed by a
 // BSD-style license that can be found in the LICENSE file.
 //
 // Modified by the Subzero authors.
 //
 //===----------------------------------------------------------------------===//
 //
@@ skipping 84 matching lines @@
 
 // Div instruction register field encodings.
 static constexpr IValueT kDivRdShift = 16;
 static constexpr IValueT kDivRmShift = 8;
 static constexpr IValueT kDivRnShift = 0;
 
 // Type of instruction encoding (bits 25-27). See ARM section A5.1
 static constexpr IValueT kInstTypeDataRegister = 0;  // i.e. 000
 static constexpr IValueT kInstTypeDataImmediate = 1; // i.e. 001
 static constexpr IValueT kInstTypeMemImmediate = 2;  // i.e. 010
+static constexpr IValueT kInstTypeRegisterShift = 3; // i.e. 011
 
 // Offset modifier to current PC for next instruction.  The offset is off by 8
 // due to the way the ARM CPUs read PC.
 static constexpr IOffsetT kPCReadOffset = 8;
 
 // Mask to pull out PC offset from branch (b) instruction.
 static constexpr int kBranchOffsetBits = 24;
 static constexpr IOffsetT kBranchOffsetMask = 0x00ffffff;
 
 inline IValueT encodeBool(bool B) { return B ? 1 : 0; }
@@ skipping 65 matching lines @@
 enum DecodedResult {
   // Unable to decode, value left undefined.
   CantDecode = 0,
   // Value is register found.
   DecodedAsRegister,
   // Value=rrrriiiiiiii where rrrr is the rotation, and iiiiiiii is the imm8
   // value.
   DecodedAsRotatedImm8,
   // i.e. 0000000pu0w0nnnn0000iiiiiiiiiiii where nnnn is the base register Rn,
   // p=1 if pre-indexed addressing, u=1 if offset positive, w=1 if writeback to
-  // Rn should be used, and iiiiiiiiiiii is the offset.
+  // Rn should be used, and iiiiiiiiiiii defines the rotated Imm8 value.
   DecodedAsImmRegOffset,
+  // i.e. 0000000pu0w00nnnnttttiiiiiss0mmmm where nnnn is the base register Rn,
+  // mmmm is the index register Rm, iiiii is the shift amount, ss is the shift
+  // kind, p=1 if pre-indexed addressing, u=1 if offset positive, and w=1 if
+  // writeback to Rn.
+  DecodedAsShiftRotateImm5,
   // Value is 32bit integer constant.
   DecodedAsConstI32
 };
 
 // Sets Encoding to a rotated Imm8 encoding of Value, if possible.
 inline IValueT encodeRotatedImm8(IValueT RotateAmt, IValueT Immed8) {
   assert(RotateAmt < (1 << kRotateBits));
   assert(Immed8 < (1 << kImmed8Bits));
   return (RotateAmt << kRotateShift) | (Immed8 << kImmed8Shift);
 }
@@ skipping 54 matching lines @@
     if (BaseRegNum == Variable::NoRegister) {
       BaseRegNum = TInfo.FrameOrStackReg;
       if (!TInfo.HasFramePointer)
         Offset += TInfo.StackAdjustment;
     }
     Value = decodeImmRegOffset(decodeGPRRegister(BaseRegNum), Offset,
                                OperandARM32Mem::Offset);
     return DecodedAsImmRegOffset;
   }
   if (const auto *Mem = llvm::dyn_cast<OperandARM32Mem>(Opnd)) {
-    if (Mem->isRegReg())
-      // TODO(kschimpf) Add this case.
-      return CantDecode;
     Variable *Var = Mem->getBase();
     if (!Var->hasReg())
       return CantDecode;
+    IValueT Rn = Var->getRegNum();
+    if (Mem->isRegReg()) {
+      const Variable *Index = Mem->getIndex();
+      if (Var == nullptr)
+        return CantDecode;
+      Value = (Rn << kRnShift) | Mem->getAddrMode() |
+              encodeShiftRotateImm5(Index->getRegNum(), Mem->getShiftOp(),
+                                    Mem->getShiftAmt());
+      return DecodedAsShiftRotateImm5;
+    }
+    // Decoded as immediate register offset.
     ConstantInteger32 *Offset = Mem->getOffset();
-    Value = decodeImmRegOffset(decodeGPRRegister(Var->getRegNum()),
-                               Offset->getValue(), Mem->getAddrMode());
+    Value = decodeImmRegOffset(decodeGPRRegister(Rn), Offset->getValue(),
+                               Mem->getAddrMode());
     return DecodedAsImmRegOffset;
   }
   return CantDecode;
 }
 
 // Checks that Offset can fit in imm24 constant of branch (b) instruction.
 bool canEncodeBranchOffset(IOffsetT Offset) {
   return Utils::IsAligned(Offset, 4) &&
          Utils::IsInt(kBranchOffsetBits, Offset >> 2);
 }
@@ skipping 431 matching lines @@
   //   eor{s}<c> <Rd>, <Rn>, #RotatedImm8
   //
   // cccc0010001snnnnddddiiiiiiiiiiii where cccc=Cond, dddd=Rd, nnnn=Rn,
   // s=SetFlags and iiiiiiiiiiii=Src1Value defining RotatedImm8.
   constexpr IValueT Eor = B0; // 0001
   emitType01(Eor, OpRd, OpRn, OpSrc1, SetFlags, Cond);
 }
 
 void AssemblerARM32::ldr(const Operand *OpRt, const Operand *OpAddress,
                          CondARM32::Cond Cond, const TargetInfo &TInfo) {
+  constexpr bool IsLoad = true;
   IValueT Rt;
   if (decodeOperand(OpRt, Rt) != DecodedAsRegister)
     return setNeedsTextFixup();
-  IValueT Address;
-  if (decodeAddress(OpAddress, Address, TInfo) != DecodedAsImmRegOffset)
-    return setNeedsTextFixup();
-  // LDR (immediate) - ARM section A8.8.63, encoding A1:
-  //   ldr<c> <Rt>, [<Rn>{, #+/-<imm12>}]      ; p=1, w=0
-  //   ldr<c> <Rt>, [<Rn>], #+/-<imm12>        ; p=1, w=1
-  //   ldr<c> <Rt>, [<Rn>, #+/-<imm12>]!       ; p=0, w=1
-  //
-  // LDRB (immediate) - ARM section A8.8.68, encoding A1:
-  //   ldrb<c> <Rt>, [<Rn>{, #+/-<imm12>}]     ; p=1, w=0
-  //   ldrb<c> <Rt>, [<Rn>], #+/-<imm12>       ; p=1, w=1
-  //   ldrb<c> <Rt>, [<Rn>, #+/-<imm12>]!      ; p=0, w=1
-  //
-  // cccc010pubw1nnnnttttiiiiiiiiiiii where cccc=Cond, tttt=Rt, nnnn=Rn,
-  // iiiiiiiiiiii=imm12, b=1 if STRB, u=1 if +.
-  constexpr bool IsLoad = true;
   const Type Ty = OpRt->getType();
   if (!(Ty == IceType_i32 || Ty == IceType_i8)) // TODO(kschimpf) Expand?
     return setNeedsTextFixup();
   const bool IsByte = isByteSizedType(Ty);
-  // Check conditions of rules violated.
-  if (getGPRReg(kRnShift, Address) == RegARM32::Encoded_Reg_pc)
+  IValueT Address;
+  switch (decodeAddress(OpAddress, Address, TInfo)) {
+  default:
     return setNeedsTextFixup();
-  if (!isBitSet(P, Address) && isBitSet(W, Address))
-    return setNeedsTextFixup();
-  if (!IsByte && (getGPRReg(kRnShift, Address) == RegARM32::Encoded_Reg_sp) &&
-      !isBitSet(P, Address) && isBitSet(U, Address) & !isBitSet(W, Address) &&
-      (mask(Address, kImm12Shift, kImmed12Bits) == 0x8 /* 000000000100 */))
-    return setNeedsTextFixup();
-  emitMemOp(Cond, kInstTypeMemImmediate, IsLoad, IsByte, Rt, Address);
+  case DecodedAsImmRegOffset: {
+    // LDR (immediate) - ARM section A8.8.63, encoding A1:
+    //   ldr<c> <Rt>, [<Rn>{, #+/-<imm12>}]      ; p=1, w=0
+    //   ldr<c> <Rt>, [<Rn>], #+/-<imm12>        ; p=1, w=1
+    //   ldr<c> <Rt>, [<Rn>, #+/-<imm12>]!       ; p=0, w=1
+    //
+    // LDRB (immediate) - ARM section A8.8.68, encoding A1:
+    //   ldrb<c> <Rt>, [<Rn>{, #+/-<imm12>}]     ; p=1, w=0
+    //   ldrb<c> <Rt>, [<Rn>], #+/-<imm12>       ; p=1, w=1
+    //   ldrb<c> <Rt>, [<Rn>, #+/-<imm12>]!      ; p=0, w=1
+    //
+    // cccc010pubw1nnnnttttiiiiiiiiiiii where cccc=Cond, tttt=Rt, nnnn=Rn,
+    // iiiiiiiiiiii=imm12, b=1 if LDRB, u=1 if +, pu0w is a BlockAddr, and
+    // pu0w0nnnn0000iiiiiiiiiiii=Address.
+
+    RegARM32::GPRRegister Rn = getGPRReg(kRnShift, Address);
+
+    // Check if conditions of rules violated.
+    if (Rn == RegARM32::Encoded_Reg_pc)
+      return setNeedsTextFixup();
+    if (!isBitSet(P, Address) && isBitSet(W, Address))
+      return setNeedsTextFixup();
+    if (!IsByte && (Rn == RegARM32::Encoded_Reg_sp) && !isBitSet(P, Address) &&
+        isBitSet(U, Address) & !isBitSet(W, Address) &&
+        (mask(Address, kImm12Shift, kImmed12Bits) == 0x8 /* 000000000100 */))
+      return setNeedsTextFixup();
+
+    return emitMemOp(Cond, kInstTypeMemImmediate, IsLoad, IsByte, Rt, Address);
+  }
+  case DecodedAsShiftRotateImm5: {
+    // LDR (register) - ARM section A8.8.66, encoding A1:
+    //   ldr<c> <Rt>, [<Rn>, +/-<Rm>{, <shift>}]{!}
+    //   ldr<c> <Rt>, [<Rn>], +/-<Rm>{, <shift>}
+    //
+    // LDRB (register) - ARM section A8.8.70, encoding A1:
+    //   ldrb<c> <Rt>, [<Rn>, +/-<Rm>{, <shift>}]{!}
+    //   ldrb<c> <Rt>, [<Rn>], +-<Rm>{, <shift>}
+    //
+    // cccc011pubw1nnnnttttiiiiiss0mmmm where cccc=Cond, tttt=Rt,
+    // b=1 if LDRB, U=1 if +, pu0b is a BlockAddr, and
+    // pu0w0nnnn0000iiiiiss0mmmm=Address.
+
+    RegARM32::GPRRegister Rn = getGPRReg(kRnShift, Address);
+    RegARM32::GPRRegister Rm = getGPRReg(kRmShift, Address);
+
+    // Check if conditions of rules violated.
+    if (isBitSet(P, Address) && isBitSet(W, Address))
+      // Instruction LDRBT!
+      return setNeedsTextFixup();
+    if (IsByte &&
+        ((Rt == RegARM32::Encoded_Reg_pc) || (Rm == RegARM32::Encoded_Reg_pc)))
+      // Unpredictable.
+      return setNeedsTextFixup();
+    if (!IsByte && Rm == RegARM32::Encoded_Reg_pc)
+      // Unpredictable.
+      return setNeedsTextFixup();
+    if (isBitSet(W, Address) &&
+        ((Rn == RegARM32::Encoded_Reg_pc) || encodeGPRRegister(Rn) == Rt))
+      // Unpredictable
+      return setNeedsTextFixup();
+
+    return emitMemOp(Cond, kInstTypeRegisterShift, IsLoad, IsByte, Rt, Address);
+  }
+  }
 }
 
 void AssemblerARM32::mov(const Operand *OpRd, const Operand *OpSrc,
                          CondARM32::Cond Cond) {
   // MOV (register) - ARM section A8.8.104, encoding A1:
   //   mov{S}<c> <Rd>, <Rn>
   //
   // cccc0001101s0000dddd00000000mmmm where cccc=Cond, s=SetFlags, dddd=Rd,
   // and nnnn=Rn.
   //
@@ skipping 416 matching lines @@
     // rr defined (RotationValue) rotate.
     constexpr IValueT Opcode = B26 | B25 | B23 | B22 | B21 | B20;
     emitUxt(Cond, Opcode, Rd, Rn, Rm, Rotation);
     return;
   }
   }
 }
 
 } // end of namespace ARM32
 } // end of namespace Ice