Subzero. ARM32. Removing memory legalization warts.

src/IceTargetLoweringARM32.h

 //===- subzero/src/IceTargetLoweringARM32.h - ARM32 lowering ----*- C++ -*-===//
 //
 //                        The Subzero Code Generator
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 ///
 /// \file
@@ skipping 117 matching lines @@
   void emit(const ConstantFloat *C) const final;
   void emit(const ConstantDouble *C) const final;
 
   void lowerArguments() override;
   void addProlog(CfgNode *Node) override;
   void addEpilog(CfgNode *Node) override;
 
   Operand *loOperand(Operand *Operand);
   Operand *hiOperand(Operand *Operand);
   void finishArgumentLowering(Variable *Arg, Variable *FramePtr,
-                              size_t BasicFrameOffset, size_t &InArgsSizeBytes);
+                              size_t BasicFrameOffset, size_t *InArgsSizeBytes);
 
   bool hasCPUFeature(TargetARM32Features::ARM32InstructionSet I) const {
     return CPUFeatures.hasFeature(I);
   }
 
   enum OperandLegalization {
     Legal_None = 0,
     Legal_Reg = 1 << 0,  /// physical register, not stack location
     Legal_Flex = 1 << 1, /// A flexible operand2, which can hold rotated small
                          /// immediates, shifted registers, or modified fp imm.
@@ skipping 228 matching lines @@
   /// all types (integer, floating point, and vectors), as well as moves between
   /// Core and VFP registers. This is not a panacea: you must obey the (weird,
   /// confusing, non-uniform) rules for data moves in ARM.
   void _mov(Variable *Dest, Operand *Src0,
             CondARM32::Cond Pred = CondARM32::AL) {
     // _mov used to be unique in the sense that it would create a temporary
     // automagically if Dest was nullptr. It won't do that anymore, so we keep
     // an assert around just in case there is some untested code path where Dest
     // is nullptr.
     assert(Dest != nullptr);
+    assert(!llvm::isa<OperandARM32Mem>(Src0));
     auto *Instr = InstARM32Mov::create(Func, Dest, Src0, Pred);
 
     Context.insert(Instr);
     if (Instr->isMultiDest()) {
       // If Instr is multi-dest, then Dest must be a Variable64On32. We add a
       // fake-def for Instr.DestHi here.
       assert(llvm::isa<Variable64On32>(Dest));
       Context.insert(InstFakeDef::create(Func, Instr->getDestHi()));
     }
   }
@@ skipping 390 matching lines @@
     Context.insert(InstARM32Vdiv::create(Func, Dest, Src0, Src1));
   }
   void _vcmp(Variable *Src0, Variable *Src1,
              CondARM32::Cond Pred = CondARM32::AL) {
     Context.insert(InstARM32Vcmp::create(Func, Src0, Src1, Pred));
   }
   void _vcmp(Variable *Src0, OperandARM32FlexFpZero *FpZero,
              CondARM32::Cond Pred = CondARM32::AL) {
     Context.insert(InstARM32Vcmp::create(Func, Src0, FpZero, Pred));
   }
+  void _veor(Variable *Dest, Variable *Src0, Variable *Src1) {
+    Context.insert(InstARM32Veor::create(Func, Dest, Src0, Src1));
+  }
   void _vmrs(CondARM32::Cond Pred = CondARM32::AL) {
     Context.insert(InstARM32Vmrs::create(Func, Pred));
   }
   void _vmul(Variable *Dest, Variable *Src0, Variable *Src1) {
     Context.insert(InstARM32Vmul::create(Func, Dest, Src0, Src1));
   }
-  void _veor(Variable *Dest, Variable *Src0, Variable *Src1) {
-    Context.insert(InstARM32Veor::create(Func, Dest, Src0, Src1));
-  }
   void _vsqrt(Variable *Dest, Variable *Src,
               CondARM32::Cond Pred = CondARM32::AL) {
     Context.insert(InstARM32Vsqrt::create(Func, Dest, Src, Pred));
   }
   void _vsub(Variable *Dest, Variable *Src0, Variable *Src1) {
     Context.insert(InstARM32Vsub::create(Func, Dest, Src0, Src1));
   }
 
   /// Run a pass through stack variables and ensure that the offsets are legal.
   /// If the offset is not legal, use a new base register that accounts for the
   /// offset, such that the addressing mode offset bits are now legal.
   void legalizeStackSlots();
   /// Returns true if the given Offset can be represented in a ldr/str.
   bool isLegalMemOffset(Type Ty, int32_t Offset) const;
   // Creates a new Base register centered around
   // [OrigBaseReg, +/- Offset+StackAdjust].
   Variable *newBaseRegister(int32_t Offset, int32_t StackAdjust,
                             Variable *OrigBaseReg);
-  /// Creates a new, legal StackVariable w.r.t. ARM's Immediate requirements.
-  /// This method is not very smart: it will always create and return a new
-  /// StackVariable, even if Offset + StackAdjust is encodable.
-  StackVariable *legalizeStackSlot(Type Ty, int32_t Offset, int32_t StackAdjust,
-                                   Variable *OrigBaseReg, Variable **NewBaseReg,
-                                   int32_t *NewBaseOffset);
-  /// Legalizes Mov if its Source (or Destination) contains an invalid
-  /// immediate.
-  void legalizeMovStackAddrImm(InstARM32Mov *Mov, int32_t StackAdjust,
-                               Variable *OrigBaseReg, Variable **NewBaseReg,
-                               int32_t *NewBaseOffset);
+  /// Creates a new, legal OperandARM32Mem for accessing OrigBase + Offset +
+  /// StackAdjust. The returned mem operand is a legal operand for accessing
+  /// memory that is of type Ty.
+  ///
+  /// If [OrigBaseReg, #Offset+StackAdjust] is encodable, then the method
+  /// returns a Mem operand expressing it. Otherwise,
+  ///
+  /// if [*NewBaseReg, #Offset+StackAdjust-*NewBaseOffset] is encodable, the
+  /// method will return that. Otherwise,
+  ///
+  /// a new base register ip=OrigBaseReg+Offset+StackAdjust is created, and the
+  /// method returns [ip, #0].
+  OperandARM32Mem *createMemOperand(Type Ty, int32_t Offset,
+                                    int32_t StackAdjust, Variable *OrigBaseReg,
+                                    Variable **NewBaseReg,
+                                    int32_t *NewBaseOffset);
+  /// Legalizes Mov if its Source (or Destination) is a spilled Variable. Moves
+  /// to memory become store instructions, and moves from memory, loads.
+  void legalizeMov(InstARM32Mov *Mov, int32_t StackAdjust,
+                   Variable *OrigBaseReg, Variable **NewBaseReg,
+                   int32_t *NewBaseOffset);
 
   TargetARM32Features CPUFeatures;
   bool UsesFramePointer = false;
   bool NeedsStackAlignment = false;
   bool MaybeLeafFunc = true;
   size_t SpillAreaSizeBytes = 0;
   // TODO(jpp): std::array instead of array.
   static llvm::SmallBitVector TypeToRegisterSet[RCARM32_NUM];
   static llvm::SmallBitVector RegisterAliases[RegARM32::Reg_NUM];
   static llvm::SmallBitVector ScratchRegs;
@@ skipping 151 matching lines @@
 
 private:
   ~TargetHeaderARM32() = default;
 
   TargetARM32Features CPUFeatures;
 };
 
 } // end of namespace Ice
 
 #endif // SUBZERO_SRC_ICETARGETLOWERINGARM32_H