Add LSL (register, immediate) to ARM integrated assembler.

tests_lit/assembler/arm32/lsl.ll

Index: tests_lit/assembler/arm32/lsl.ll
diff --git a/tests_lit/assembler/arm32/blx.ll b/tests_lit/assembler/arm32/lsl.ll
similarity index 55%
copy from tests_lit/assembler/arm32/blx.ll
copy to tests_lit/assembler/arm32/lsl.ll
index 0c4f38820c87018022e7e1b6a88b785f04f0deeb..956c47c2be0ea562c7571420a0f4ae32ef474d21 100644
--- a/tests_lit/assembler/arm32/blx.ll
+++ b/tests_lit/assembler/arm32/lsl.ll
@@ -1,4 +1,4 @@
-; Show that we know how to translate add.
+; Show that we know how to translate lsl.
 
 ; NOTE: We use -O2 to get rid of memory stores.
 
@@ -20,21 +20,27 @@
 ; RUN: %p2i --filetype=iasm -i %s --target=arm32 --assemble --disassemble \
 ; RUN:   --args -O2 | FileCheck %s --check-prefix=DIS
 
-define internal void @callIndirect(i32 %addr) {
-; ASM-LABEL:callIndirect:
-; DIS-LABEL:00000000 <callIndirect>:
-; IASM-LABEL:callIndirect:
+define internal i32 @_Z8testUdivhh(i32 %a, i32 %b) {

[Jim Stichnoth, 2015/11/22 03:58:47]

What a lovely function name! :)  Of course it is actually the mangling of
"testUdiv(unsigned char, unsigned char)".  Maybe the unmangled names could be
used instead for the lit tests?

I'm actually puzzled as to how shifting gets involved in udiv, but I'm sure
there's a good explanation.  Even so, surely there could be a more direct
example than udiv?

[Karl, 2015/11/30 16:53:52]

Simplified.

+
+; ASM-LABEL:_Z8testUdivhh:
+; DIS-LABEL:00000000 <_Z8testUdivhh>:
+; IASM-LABEL:_Z8testUdivhh:
 
 entry:
-; ASM-NEXT:.LcallIndirect$entry:
-; IASM-NEXT:.LcallIndirect$entry:
+
+; ASM-NEXT:.L_Z8testUdivhh$entry:
 ; ASM-NEXT:     push    {lr}
 ; DIS-NEXT:   0:        e52de004
+; IASM-NEXT:.L_Z8testUdivhh$entry:
 ; IASM-NEXT:    .byte 0x4
 ; IASM-NEXT:    .byte 0xe0
 ; IASM-NEXT:    .byte 0x2d
 ; IASM-NEXT:    .byte 0xe5
 
+  %b.arg_trunc = trunc i32 %b to i8
+  %a.arg_trunc = trunc i32 %a to i8
+  %div3 = udiv i8 %a.arg_trunc, %b.arg_trunc
+
 ; ASM-NEXT:     sub     sp, sp, #12
 ; DIS-NEXT:   4:        e24dd00c
 ; IASM-NEXT:    .byte 0xc
@@ -42,23 +48,36 @@ entry:
 ; IASM-NEXT:    .byte 0x4d
 ; IASM-NEXT:    .byte 0xe2
 
-   %calladdr = inttoptr i32 %addr to void (i32)*
-
-; ASM-NEXT:     mov     r1, r0
-; DIS-NEXT:   8:        e1a01000
-; IASM-NEXT:    .byte 0x0
-; IASM-NEXT:    .byte 0x10
-; IASM-NEXT:    .byte 0xa0
+; ASM-NEXT:     lsls    r2, r1, #24
+; DIS-NEXT:   8:        e1b02c01
+; IASM-NEXT:    .byte 0x1
+; IASM-NEXT:    .byte 0x2c
+; IASM-NEXT:    .byte 0xb0
 ; IASM-NEXT:    .byte 0xe1
 
-   call void %calladdr(i32 %addr)
+  %div3.ret_ext = zext i8 %div3 to i32
+  ret i32 %div3.ret_ext
+}
+
+define internal i32 @_Z7testShljj(i32 %a, i32 %b) {
 
-; ASM-NEXT:     blx     r1
-; DIS-NEXT:   c:        e12fff31
-; IASM-NEXT:    .byte 0x31
-; IASM-NEXT:    .byte 0xff
-; IASM-NEXT:    .byte 0x2f
+; ASM-LABEL:_Z7testShljj:
+; DIS-LABEL:00000030 <_Z7testShljj>:
+; IASM-LABEL:_Z7testShljj:
+
+entry:
+
+; ASM-NEXT:.L_Z7testShljj$entry:
+; IASM-NEXT:.L_Z7testShljj$entry:
+
+  %shl = shl i32 %a, %b
+
+; ASM-NEXT:     lsl     r0, r0, r1
+; DIS-NEXT:  30:        e1a00110
+; IASM-NEXT:    .byte 0x10
+; IASM-NEXT:    .byte 0x1
+; IASM-NEXT:    .byte 0xa0
 ; IASM-NEXT:    .byte 0xe1
 
-   ret void
+  ret i32 %shl
 }