Add LSL (register, immediate) to ARM integrated assembler.

src/IceAssemblerARM32.h

 //===- subzero/src/IceAssemblerARM32.h - Assembler for ARM32 ----*- C++ -*-===//
 //
 // Copyright (c) 2013, the Dart project authors.  Please see the AUTHORS file
 // for details. All rights reserved. Use of this source code is governed by a
 // BSD-style license that can be found in the LICENSE file.
 //
 // Modified by the Subzero authors.
 //
 //===----------------------------------------------------------------------===//
 //
@@ skipping 205 matching lines @@
 
   void ldr(const Operand *OpRt, const Operand *OpAddress, CondARM32::Cond Cond,
            const TargetInfo &TInfo);
 
   void ldr(const Operand *OpRt, const Operand *OpAddress, CondARM32::Cond Cond,
            const TargetLowering *Lowering) {
     const TargetInfo TInfo(Lowering);
     ldr(OpRt, OpAddress, Cond, TInfo);
   }
 
+  void lsl(const Operand *OpRd, const Operand *OpRn, const Operand *OpSrc1,
+           bool SetFlags, CondARM32::Cond Cond);
+
   void mov(const Operand *OpRd, const Operand *OpSrc, CondARM32::Cond Cond);
 
   void movw(const Operand *OpRd, const Operand *OpSrc, CondARM32::Cond Cond);
 
   void movt(const Operand *OpRd, const Operand *OpSrc, CondARM32::Cond Cond);
 
   void mla(const Operand *OpRd, const Operand *OpRn, const Operand *OpRm,
            const Operand *OpRa, CondARM32::Cond Cond);
 
   void mul(const Operand *OpRd, const Operand *OpRn, const Operand *OpSrc1,
@@ skipping 69 matching lines @@
     DB_W = (8 | 0 | 1) << 21, // decrement before with writeback to base
     IB_W = (8 | 4 | 1) << 21  // increment before with writeback to base
   };
 
   Label *getOrCreateLabel(SizeT Number, LabelVector &Labels);
 
   void bindCfgNodeLabel(const CfgNode *Node) override;
 
   void emitInst(IValueT Value) { Buffer.emit<IValueT>(Value); }
 
+  // List of possible checks to apply when calling emitType01() (below).
+  enum EmitChecks { NoChecks, RdIsPcAndSetFlags };
+
   // Pattern cccctttoooosnnnnddddiiiiiiiiiiii where cccc=Cond, ttt=Type,
-  // oooo=Opcode, nnnn=Rn, dddd=Rd, iiiiiiiiiiii=imm12 (See ARM section A5.2.3).
+  // s=SetFlags, oooo=Opcode, nnnn=Rn, dddd=Rd, iiiiiiiiiiii=imm12 (See ARM
+  // section A5.2.3).
   void emitType01(CondARM32::Cond Cond, IValueT Type, IValueT Opcode,
-                  bool SetCc, IValueT Rn, IValueT Rd, IValueT imm12);
-
-  // List of possible checks to apply when calling emitType01() (below).
-  enum Type01Checks {
-    NoChecks,
-    RdIsPcAndSetFlags,
-  };
+                  bool SetFlags, IValueT Rn, IValueT Rd, IValueT imm12,
+                  EmitChecks RuleChecks);
 
   // Converts appropriate representation on a data operation, and then calls
   // emitType01 above.
   void emitType01(IValueT Opcode, const Operand *OpRd, const Operand *OpRn,
                   const Operand *OpSrc1, bool SetFlags, CondARM32::Cond Cond,
-                  Type01Checks RuleChecks = RdIsPcAndSetFlags);
+                  EmitChecks RuleChecks);
 
   // Same as above, but the value for Rd and Rn have already been converted
   // into instruction values.
   void emitType01(IValueT Opcode, IValueT OpRd, IValueT OpRn,
                   const Operand *OpSrc1, bool SetFlags, CondARM32::Cond Cond,
-                  Type01Checks RuleChecks = RdIsPcAndSetFlags);
+                  EmitChecks RuleChecks);
 
   void emitType05(CondARM32::Cond COnd, int32_t Offset, bool Link);
 
   // Pattern ccccoooaabalnnnnttttaaaaaaaaaaaa where cccc=Cond, ooo=InstType,
   // l=isLoad, b=isByte, and aaa0a0aaaa0000aaaaaaaaaaaa=Address. Note that
   // Address is assumed to be defined by decodeAddress() in
   // IceAssemblerARM32.cpp.
   void emitMemOp(CondARM32::Cond Cond, IValueT InstType, bool IsLoad,
                  bool IsByte, uint32_t Rt, uint32_t Address);
 
   // Pattern cccc100aaaalnnnnrrrrrrrrrrrrrrrr where cccc=Cond,
   // aaaa<<21=AddressMode, l=IsLoad, nnnn=BaseReg, and
   // rrrrrrrrrrrrrrrr is bitset of Registers.
   void emitMultiMemOp(CondARM32::Cond Cond, BlockAddressMode AddressMode,
                       bool IsLoad, IValueT BaseReg, IValueT Registers);
 
   // Pattern cccc011100x1dddd1111mmmm0001nnn where cccc=Cond,
   // x=Opcode, dddd=Rd, nnnn=Rn, mmmm=Rm.
   void emitDivOp(CondARM32::Cond Cond, IValueT Opcode, IValueT Rd, IValueT Rn,
                  IValueT Rm);
 
   // Pattern ccccxxxxxxxfnnnnddddssss1001mmmm where cccc=Cond, dddd=Rd, nnnn=Rn,
-  // mmmm=Rm, ssss=Rs, f=SetCc, and xxxxxxx=Opcode.
+  // mmmm=Rm, ssss=Rs, f=SetFlags and xxxxxxx=Opcode.
   void emitMulOp(CondARM32::Cond Cond, IValueT Opcode, IValueT Rd, IValueT Rn,
-                 IValueT Rm, IValueT Rs, bool SetCc);
+                 IValueT Rm, IValueT Rs, bool SetFlags);
 
   // Implements various forms of Unsigned extend value, using pattern
   // ccccxxxxxxxxnnnnddddrr000111mmmm where cccc=Cond, xxxxxxxx<<20=Opcode,
   // nnnn=Rn, dddd=Rd, rr=Rotation, and mmmm=Rm.
   void emitUxt(CondARM32::Cond, IValueT Opcode, IValueT Rd, IValueT Rn,
                IValueT Rm, RotationValue Rotation);
 
   // Pattern cccctttxxxxnnnn0000iiiiiiiiiiii where cccc=Cond, nnnn=Rn,
   // ttt=Instruction type (derived from OpSrc1), iiiiiiiiiiii is derived from
   // OpSrc1, and xxxx=Opcode.
@@ skipping 12 matching lines @@
   // cccc=Cond, xxxxxxx<<21=Opcode, dddd=Rd, s=SetFlags, and
   // iiiiiiiiiiiiiiii=Imm16.
   void emitMovw(IValueT Opcode, IValueT Rd, IValueT Imm16, bool SetFlags,
                 CondARM32::Cond Cond);
 };
 
 } // end of namespace ARM32
 } // end of namespace Ice
 
 #endif // SUBZERO_SRC_ICEASSEMBLERARM32_H