Add LSL (register, immediate) to ARM integrated assembler.

src/IceAssemblerARM32.cpp

 //===- subzero/src/IceAssemblerARM32.cpp - Assembler for ARM32 --*- C++ -*-===//
 //
 // Copyright (c) 2013, the Dart project authors.  Please see the AUTHORS file
 // for details. All rights reserved. Use of this source code is governed by a
 // BSD-style license that can be found in the LICENSE file.
 //
 // Modified by the Subzero authors.
 //
 //===----------------------------------------------------------------------===//
 //
@@ skipping 82 matching lines @@
 // Rotation instructions (uxtb etc.).
 static constexpr IValueT kRotationShift = 10;
 
 // Div instruction register field encodings.
 static constexpr IValueT kDivRdShift = 16;
 static constexpr IValueT kDivRmShift = 8;
 static constexpr IValueT kDivRnShift = 0;
 
 // Type of instruction encoding (bits 25-27). See ARM section A5.1
 static constexpr IValueT kInstTypeDataRegister = 0;  // i.e. 000
+static constexpr IValueT kInstTypeDataRegShift = 0;  // i.e. 000
 static constexpr IValueT kInstTypeDataImmediate = 1; // i.e. 001
 static constexpr IValueT kInstTypeMemImmediate = 2;  // i.e. 010
 static constexpr IValueT kInstTypeRegisterShift = 3; // i.e. 011
 
 // Offset modifier to current PC for next instruction.  The offset is off by 8
 // due to the way the ARM CPUs read PC.
 static constexpr IOffsetT kPCReadOffset = 8;
 
 // Mask to pull out PC offset from branch (b) instruction.
 static constexpr int kBranchOffsetBits = 24;
@@ skipping 75 matching lines @@
   DecodedAsRotatedImm8,
   // i.e. 0000000pu0w0nnnn0000iiiiiiiiiiii where nnnn is the base register Rn,
   // p=1 if pre-indexed addressing, u=1 if offset positive, w=1 if writeback to
   // Rn should be used, and iiiiiiiiiiii defines the rotated Imm8 value.
   DecodedAsImmRegOffset,
   // i.e. 0000000pu0w00nnnnttttiiiiiss0mmmm where nnnn is the base register Rn,
   // mmmm is the index register Rm, iiiii is the shift amount, ss is the shift
   // kind, p=1 if pre-indexed addressing, u=1 if offset positive, and w=1 if
   // writeback to Rn.
   DecodedAsShiftRotateImm5,
+  // i.e. 000000000000000000000iiiii0000000 iiii defines Imm5 value to shift.
+  DecodedAsShiftImm5,
   // Value is 32bit integer constant.
   DecodedAsConstI32
 };
 
 // Sets Encoding to a rotated Imm8 encoding of Value, if possible.
 inline IValueT encodeRotatedImm8(IValueT RotateAmt, IValueT Immed8) {
   assert(RotateAmt < (1 << kRotateBits));
   assert(Immed8 < (1 << kImmed8Bits));
   return (RotateAmt << kRotateShift) | (Immed8 << kImmed8Shift);
 }
 
 // Encodes iiiiitt0mmmm for data-processing (2nd) operands where iiiii=Imm5,
 // tt=Shift, and mmmm=Rm.
 IValueT encodeShiftRotateImm5(IValueT Rm, OperandARM32::ShiftKind Shift,
                               IOffsetT imm5) {
   (void)kShiftImmBits;
   assert(imm5 < (1 << kShiftImmBits));
   return (imm5 << kShiftImmShift) | (encodeShift(Shift) << kShiftShift) | Rm;
 }
 
+// Encodes mmmmtt01ssss for data-processing (2nd) operands where mmmm=Rm,
+// ssss=Rs, and tt=Shift.
+IValueT encodeShiftRotateReg(IValueT Rm, OperandARM32::ShiftKind Shift,
+                             IValueT Rs) {
+  return (Rs << kRsShift) | (encodeShift(Shift) << kShiftShift) | B4 |
+         (Rm << kRmShift);
+}
+
 DecodedResult decodeOperand(const Operand *Opnd, IValueT &Value) {
   if (const auto *Var = llvm::dyn_cast<Variable>(Opnd)) {
     if (Var->hasReg()) {
       Value = Var->getRegNum();
       return DecodedAsRegister;
     }
-  } else if (const auto *FlexImm = llvm::dyn_cast<OperandARM32FlexImm>(Opnd)) {
+    return CantDecode;
+  }
+  if (const auto *FlexImm = llvm::dyn_cast<OperandARM32FlexImm>(Opnd)) {
     const IValueT Immed8 = FlexImm->getImm();
     const IValueT Rotate = FlexImm->getRotateAmt();
     if (!((Rotate < (1 << kRotateBits)) && (Immed8 < (1 << kImmed8Bits))))
       return CantDecode;
     Value = (Rotate << kRotateShift) | (Immed8 << kImmed8Shift);
     return DecodedAsRotatedImm8;
   }
   if (const auto *Const = llvm::dyn_cast<ConstantInteger32>(Opnd)) {
     Value = Const->getValue();
     return DecodedAsConstI32;
   }
+  if (const auto *ShImm = llvm::dyn_cast<OperandARM32ShAmtImm>(Opnd)) {
+    const IValueT Immed5 = ShImm->getShAmtImm();
+    assert(Immed5 < (1 << kShiftImmBits));
+    Value = (Immed5 << kShiftImmShift);
+    return DecodedAsShiftImm5;
+  }
   return CantDecode;
 }
 
 IValueT decodeImmRegOffset(RegARM32::GPRRegister Reg, IOffsetT Offset,
                            OperandARM32Mem::AddrMode Mode) {
   IValueT Value = Mode | (encodeGPRRegister(Reg) << kRnShift);
   if (Offset < 0) {
     Value = (Value ^ U) | -Offset; // Flip U to adjust sign.
   } else {
     Value |= Offset;
@@ skipping 170 matching lines @@
 void AssemblerARM32::emitTextInst(const std::string &Text, SizeT InstSize) {
   AssemblerFixup *F = createTextFixup(Text, InstSize);
   emitFixup(F);
   for (SizeT I = 0; I < InstSize; ++I) {
     AssemblerBuffer::EnsureCapacity ensured(&Buffer);
     Buffer.emit<char>(0);
   }
 }
 
 void AssemblerARM32::emitType01(CondARM32::Cond Cond, IValueT Type,
-                                IValueT Opcode, bool SetCc, IValueT Rn,
-                                IValueT Rd, IValueT Imm12) {
+                                IValueT Opcode, bool SetFlags, IValueT Rn,
+                                IValueT Rd, IValueT Imm12,
+                                EmitChecks RuleChecks) {
+  switch (RuleChecks) {
+  case NoChecks:
+    break;
+  case RdIsPcAndSetFlags:
+    if (((Rd == RegARM32::Encoded_Reg_pc) && SetFlags))

[Jim Stichnoth, 2015/11/22 03:58:47]

Maybe strip one level of parens?

[Karl, 2015/11/30 16:53:52]

Done.

+      // Conditions of rule violated.
+      return setNeedsTextFixup();
+    break;
+  }
+
   if (!isGPRRegisterDefined(Rd) || !isConditionDefined(Cond))
     return setNeedsTextFixup();
   AssemblerBuffer::EnsureCapacity ensured(&Buffer);
   const IValueT Encoding = (encodeCondition(Cond) << kConditionShift) |
                            (Type << kTypeShift) | (Opcode << kOpcodeShift) |
-                           (encodeBool(SetCc) << kSShift) | (Rn << kRnShift) |
-                           (Rd << kRdShift) | Imm12;
+                           (encodeBool(SetFlags) << kSShift) |
+                           (Rn << kRnShift) | (Rd << kRdShift) | Imm12;
   emitInst(Encoding);
 }
 
 void AssemblerARM32::emitType01(IValueT Opcode, const Operand *OpRd,
                                 const Operand *OpRn, const Operand *OpSrc1,
                                 bool SetFlags, CondARM32::Cond Cond,
-                                Type01Checks RuleChecks) {
+                                EmitChecks RuleChecks) {
   IValueT Rd;
   if (decodeOperand(OpRd, Rd) != DecodedAsRegister)
     return setNeedsTextFixup();
   IValueT Rn;
   if (decodeOperand(OpRn, Rn) != DecodedAsRegister)
     return setNeedsTextFixup();
   emitType01(Opcode, Rd, Rn, OpSrc1, SetFlags, Cond, RuleChecks);
 }
 
 void AssemblerARM32::emitType01(IValueT Opcode, IValueT Rd, IValueT Rn,
                                 const Operand *OpSrc1, bool SetFlags,
-                                CondARM32::Cond Cond, Type01Checks RuleChecks) {
+                                CondARM32::Cond Cond, EmitChecks RuleChecks) {
   switch (RuleChecks) {
   case NoChecks:
     break;
   case RdIsPcAndSetFlags:
     if (((Rd == RegARM32::Encoded_Reg_pc) && SetFlags))
       // Conditions of rule violated.
       return setNeedsTextFixup();
     break;
   }
 
   IValueT Src1Value;
   // TODO(kschimpf) Other possible decodings of data operations.
   switch (decodeOperand(OpSrc1, Src1Value)) {
   default:
     return setNeedsTextFixup();
   case DecodedAsRegister: {
     // XXX (register)
     //   xxx{s}<c> <Rd>, <Rn>, <Rm>{, <shiff>}
     //
     // cccc0000100snnnnddddiiiiitt0mmmm where cccc=Cond, dddd=Rd, nnnn=Rn,
     // mmmm=Rm, iiiii=Shift, tt=ShiftKind, and s=SetFlags.
     constexpr IValueT Imm5 = 0;
     Src1Value = encodeShiftRotateImm5(Src1Value, OperandARM32::kNoShift, Imm5);
-    emitType01(Cond, kInstTypeDataRegister, Opcode, SetFlags, Rn, Rd,
-               Src1Value);
+    emitType01(Cond, kInstTypeDataRegister, Opcode, SetFlags, Rn, Rd, Src1Value,
+               RuleChecks);
     return;
   }
   case DecodedAsConstI32: {
     // See if we can convert this to an XXX (immediate).
     IValueT RotateAmt;
     IValueT Imm8;
     if (!OperandARM32FlexImm::canHoldImm(Src1Value, &RotateAmt, &Imm8))
       return setNeedsTextFixup();
     Src1Value = encodeRotatedImm8(RotateAmt, Imm8);
     // Intentionally fall to next case!
   }
   case DecodedAsRotatedImm8: {
     // XXX (Immediate)
     //   xxx{s}<c> <Rd>, <Rn>, #<RotatedImm8>
     //
     // cccc0010100snnnnddddiiiiiiiiiiii where cccc=Cond, dddd=Rd, nnnn=Rn,
     // s=SetFlags and iiiiiiiiiiii=Src1Value defining RotatedImm8.
     emitType01(Cond, kInstTypeDataImmediate, Opcode, SetFlags, Rn, Rd,
-               Src1Value);
+               Src1Value, RuleChecks);
     return;
   }
   }
 }
 
 void AssemblerARM32::emitType05(CondARM32::Cond Cond, IOffsetT Offset,
                                 bool Link) {
   // cccc101liiiiiiiiiiiiiiiiiiiiiiii where cccc=Cond, l=Link, and
   // iiiiiiiiiiiiiiiiiiiiiiii=
   // EncodedBranchOffset(cccc101l000000000000000000000000, Offset);
@@ skipping 62 matching lines @@
     return setNeedsTextFixup();
   AssemblerBuffer::EnsureCapacity ensured(&Buffer);
   const IValueT Encoding = Opcode | (encodeCondition(Cond) << kConditionShift) |
                            (Rn << kDivRnShift) | (Rd << kDivRdShift) | B26 |
                            B25 | B24 | B20 | B15 | B14 | B13 | B12 | B4 |
                            (Rm << kDivRmShift);
   emitInst(Encoding);
 }
 
 void AssemblerARM32::emitMulOp(CondARM32::Cond Cond, IValueT Opcode, IValueT Rd,
-                               IValueT Rn, IValueT Rm, IValueT Rs, bool SetCc) {
+                               IValueT Rn, IValueT Rm, IValueT Rs,
+                               bool SetFlags) {
   if (!isGPRRegisterDefined(Rd) || !isGPRRegisterDefined(Rn) ||
       !isGPRRegisterDefined(Rm) || !isGPRRegisterDefined(Rs) ||
       !isConditionDefined(Cond))
     return setNeedsTextFixup();
   AssemblerBuffer::EnsureCapacity ensured(&Buffer);
   IValueT Encoding = Opcode | (encodeCondition(Cond) << kConditionShift) |
-                     (encodeBool(SetCc) << kSShift) | (Rn << kRnShift) |
+                     (encodeBool(SetFlags) << kSShift) | (Rn << kRnShift) |
                      (Rd << kRdShift) | (Rs << kRsShift) | B7 | B4 |
                      (Rm << kRmShift);
   emitInst(Encoding);
 }
 
 void AssemblerARM32::emitUxt(CondARM32::Cond Cond, IValueT Opcode, IValueT Rd,
                              IValueT Rn, IValueT Rm, RotationValue Rotation) {
   IValueT Rot = encodeRotation(Rotation);
   if (!isConditionDefined(Cond) || !Utils::IsUint(2, Rot))
     return setNeedsTextFixup();
@@ skipping 26 matching lines @@
   //
   // cccc0000101snnnnddddiiiiitt0mmmm where cccc=Cond, dddd=Rd, nnnn=Rn,
   // mmmm=Rm, iiiii=Shift, tt=ShiftKind, and s=SetFlags.
   //
   // ADC (Immediate) - ARM section A8.8.1, encoding A1:
   //   adc{s}<c> <Rd>, <Rn>, #<RotatedImm8>
   //
   // cccc0010101snnnnddddiiiiiiiiiiii where cccc=Cond, dddd=Rd, nnnn=Rn,
   // s=SetFlags and iiiiiiiiiiii=Src1Value defining RotatedImm8.
   constexpr IValueT Adc = B2 | B0; // 0101
-  emitType01(Adc, OpRd, OpRn, OpSrc1, SetFlags, Cond);
+  emitType01(Adc, OpRd, OpRn, OpSrc1, SetFlags, Cond, RdIsPcAndSetFlags);
 }
 
 void AssemblerARM32::add(const Operand *OpRd, const Operand *OpRn,
                          const Operand *OpSrc1, bool SetFlags,
                          CondARM32::Cond Cond) {
   // ADD (register) - ARM section A8.8.7, encoding A1:
   //   add{s}<c> <Rd>, <Rn>, <Rm>{, <shiff>}
   // ADD (Sp plus register) - ARM section A8.8.11, encoding A1:
   //   add{s}<c> sp, <Rn>, <Rm>{, <shiff>}
   //
   // cccc0000100snnnnddddiiiiitt0mmmm where cccc=Cond, dddd=Rd, nnnn=Rn,
   // mmmm=Rm, iiiii=Shift, tt=ShiftKind, and s=SetFlags.
   //
   // ADD (Immediate) - ARM section A8.8.5, encoding A1:
   //   add{s}<c> <Rd>, <Rn>, #<RotatedImm8>
   // ADD (SP plus immediate) - ARM section A8.8.9, encoding A1.
   //   add{s}<c> <Rd>, sp, #<RotatedImm8>
   //
   // cccc0010100snnnnddddiiiiiiiiiiii where cccc=Cond, dddd=Rd, nnnn=Rn,
   // s=SetFlags and iiiiiiiiiiii=Src1Value defining RotatedImm8.
   constexpr IValueT Add = B2; // 0100
-  emitType01(Add, OpRd, OpRn, OpSrc1, SetFlags, Cond);
+  emitType01(Add, OpRd, OpRn, OpSrc1, SetFlags, Cond, RdIsPcAndSetFlags);
 }
 
 void AssemblerARM32::and_(const Operand *OpRd, const Operand *OpRn,
                           const Operand *OpSrc1, bool SetFlags,
                           CondARM32::Cond Cond) {
   // AND (register) - ARM section A8.8.14, encoding A1:
   //   and{s}<c> <Rd>, <Rn>{, <shift>}
   //
   // cccc0000000snnnnddddiiiiitt0mmmm where cccc=Cond, dddd=Rd, nnnn=Rn,
   // mmmm=Rm, iiiii=Shift, tt=ShiftKind, and s=SetFlags.
   //
   // AND (Immediate) - ARM section A8.8.13, encoding A1:
   //   and{s}<c> <Rd>, <Rn>, #<RotatedImm8>
   //
   // cccc0010100snnnnddddiiiiiiiiiiii where cccc=Cond, dddd=Rd, nnnn=Rn,
   // s=SetFlags and iiiiiiiiiiii=Src1Value defining RotatedImm8.
   constexpr IValueT And = 0; // 0000
-  emitType01(And, OpRd, OpRn, OpSrc1, SetFlags, Cond);
+  emitType01(And, OpRd, OpRn, OpSrc1, SetFlags, Cond, RdIsPcAndSetFlags);
 }
 
 void AssemblerARM32::b(Label *L, CondARM32::Cond Cond) {
   emitBranch(L, Cond, false);
 }
 
 void AssemblerARM32::bkpt(uint16_t Imm16) {
   // BKPT - ARM section A*.8.24 - encoding A1:
   //   bkpt #<Imm16>
   //
@@ skipping 12 matching lines @@
   //
   // cccc0001110snnnnddddiiiiitt0mmmm where cccc=Cond, dddd=Rd, nnnn=Rn,
   // mmmm=Rm, iiiii=Shift, tt=ShiftKind, and s=SetFlags.
   //
   // BIC (immediate) - ARM section A8.8.21, encoding A1:
   //   bic{s}<c> <Rd>, <Rn>, #<RotatedImm8>
   //
   // cccc0011110snnnnddddiiiiiiiiiiii where cccc=Cond, dddd=Rn, nnnn=Rn,
   // s=SetFlags, and iiiiiiiiiiii=Src1Value defining RotatedImm8.
   IValueT Opcode = B3 | B2 | B1; // i.e. 1110
-  emitType01(Opcode, OpRd, OpRn, OpSrc1, SetFlags, Cond);
+  emitType01(Opcode, OpRd, OpRn, OpSrc1, SetFlags, Cond, RdIsPcAndSetFlags);
 }
 
 void AssemblerARM32::bl(const ConstantRelocatable *Target) {
   // BL (immediate) - ARM section A8.8.25, encoding A1:
   //   bl<c> <label>
   //
   // cccc1011iiiiiiiiiiiiiiiiiiiiiiii where cccc=Cond (not currently allowed)
   // and iiiiiiiiiiiiiiiiiiiiiiii is the (encoded) Target to branch to.
   emitFixup(createBlFixup(Target));
   constexpr CondARM32::Cond Cond = CondARM32::AL;
@@ skipping 60 matching lines @@
   //
   // cccc0000001snnnnddddiiiiitt0mmmm where cccc=Cond, dddd=Rd, nnnn=Rn,
   // mmmm=Rm, iiiii=Shift, tt=ShiftKind, and s=SetFlags.
   //
   // EOR (Immediate) - ARM section A8.*.46, encoding A1:
   //   eor{s}<c> <Rd>, <Rn>, #RotatedImm8
   //
   // cccc0010001snnnnddddiiiiiiiiiiii where cccc=Cond, dddd=Rd, nnnn=Rn,
   // s=SetFlags and iiiiiiiiiiii=Src1Value defining RotatedImm8.
   constexpr IValueT Eor = B0; // 0001
-  emitType01(Eor, OpRd, OpRn, OpSrc1, SetFlags, Cond);
+  emitType01(Eor, OpRd, OpRn, OpSrc1, SetFlags, Cond, RdIsPcAndSetFlags);
 }
 
 void AssemblerARM32::ldr(const Operand *OpRt, const Operand *OpAddress,
                          CondARM32::Cond Cond, const TargetInfo &TInfo) {
   constexpr bool IsLoad = true;
   IValueT Rt;
   if (decodeOperand(OpRt, Rt) != DecodedAsRegister)
     return setNeedsTextFixup();
   const Type Ty = OpRt->getType();
   if (!(Ty == IceType_i32 || Ty == IceType_i8)) // TODO(kschimpf) Expand?
@@ skipping 62 matching lines @@
     if (isBitSet(W, Address) &&
         ((Rn == RegARM32::Encoded_Reg_pc) || encodeGPRRegister(Rn) == Rt))
       // Unpredictable
       return setNeedsTextFixup();
 
     return emitMemOp(Cond, kInstTypeRegisterShift, IsLoad, IsByte, Rt, Address);
   }
   }
 }
 
+void AssemblerARM32::lsl(const Operand *OpRd, const Operand *OpRm,
+                         const Operand *OpSrc1, bool SetFlags,
+                         CondARM32::Cond Cond) {
+  constexpr IValueT Lsl = B3 | B2 | B0; // 1101
+  constexpr IValueT Rn = 0;             // Rn field is not used.
+  IValueT Rd;
+  if (decodeOperand(OpRd, Rd) != DecodedAsRegister)
+    return setNeedsTextFixup();
+  IValueT Rm;
+  if (decodeOperand(OpRm, Rm) != DecodedAsRegister)
+    return setNeedsTextFixup();
+  IValueT Value;
+  switch (decodeOperand(OpSrc1, Value)) {
+  default:
+    return setNeedsTextFixup();
+  case DecodedAsShiftImm5: {
+    // LSL (immediate) - ARM section A8.8.94, encoding A1:
+    //   lsl{s}<c> <Rd>, <Rm>, #imm5
+    //
+    // cccc0001101s0000ddddiiiii000mmmm where cccc=Cond, s=SetFlags, dddd=Rd,
+    // iiiii=imm5, and mmmm=Rm.
+    Value = Value | (Rm << kRmShift);
+    emitType01(Cond, kInstTypeDataRegShift, Lsl, SetFlags, Rn, Rd, Value,
+               RdIsPcAndSetFlags);
+    return;
+  }
+  case DecodedAsRegister: {
+    // LSL (register) - ARM section A8.8.95, encoding A1:
+    //   lsl{S}<c> <Rd>, <Rm>, <Rs>
+    //
+    // cccc0001101s0000ddddssss0001mmmm where cccc=Cond, s=SetFlags, dddd=Rd,
+    // mmmm=Rm, and ssss=Rs.
+    IValueT Rs;
+    if (decodeOperand(OpSrc1, Rs) != DecodedAsRegister)
+      return setNeedsTextFixup();
+    if ((Rd == RegARM32::Encoded_Reg_pc) || (Rm == RegARM32::Encoded_Reg_pc) ||
+        (Rs == RegARM32::Encoded_Reg_pc))
+      setNeedsTextFixup();
+    emitType01(Cond, kInstTypeDataRegShift, Lsl, SetFlags, Rn, Rd,
+               encodeShiftRotateReg(Rm, OperandARM32::kNoShift, Rs), NoChecks);
+    return;
+  }
+  }
+}
+
 void AssemblerARM32::mov(const Operand *OpRd, const Operand *OpSrc,
                          CondARM32::Cond Cond) {
   // MOV (register) - ARM section A8.8.104, encoding A1:
   //   mov{S}<c> <Rd>, <Rn>
   //
   // cccc0001101s0000dddd00000000mmmm where cccc=Cond, s=SetFlags, dddd=Rd,
   // and nnnn=Rn.
   //
   // MOV (immediate) - ARM section A8.8.102, encoding A1:
   //   mov{S}<c> <Rd>, #<RotatedImm8>
   //
   // cccc0011101s0000ddddiiiiiiiiiiii where cccc=Cond, s=SetFlags, dddd=Rd,
   // and iiiiiiiiiiii=RotatedImm8=Src.  Note: We don't use movs in this
   // assembler.
   IValueT Rd;
   if (decodeOperand(OpRd, Rd) != DecodedAsRegister)
     return setNeedsTextFixup();
   constexpr bool SetFlags = false;
   constexpr IValueT Rn = 0;
   constexpr IValueT Mov = B3 | B2 | B0; // 1101.
-  emitType01(Mov, Rd, Rn, OpSrc, SetFlags, Cond);
+  emitType01(Mov, Rd, Rn, OpSrc, SetFlags, Cond, RdIsPcAndSetFlags);
 }
 
 void AssemblerARM32::emitMovw(IValueT Opcode, IValueT Rd, IValueT Imm16,
                               bool SetFlags, CondARM32::Cond Cond) {
   if (!isConditionDefined(Cond) || !Utils::IsAbsoluteUint(16, Imm16))
     return setNeedsTextFixup();
   AssemblerBuffer::EnsureCapacity ensured(&Buffer);
   const IValueT Encoding = encodeCondition(Cond) << kConditionShift | Opcode |
                            (encodeBool(SetFlags) << kSShift) |
                            ((Imm16 >> 12) << 16) | Rd << kRdShift |
@@ skipping 77 matching lines @@
   //
   // cccc0000110snnnnddddiiiiitt0mmmm where cccc=Cond, dddd=Rd, nnnn=Rn,
   // mmmm=Rm, iiiii=Shift, tt=ShiftKind, and s=SetFlags.
   //
   // SBC (Immediate) - ARM section A8.8.161, encoding A1:
   //   sbc{s}<c> <Rd>, <Rn>, #<RotatedImm8>
   //
   // cccc0010110snnnnddddiiiiiiiiiiii where cccc=Cond, dddd=Rd, nnnn=Rn,
   // s=SetFlags and iiiiiiiiiiii=Src1Value defining RotatedImm8.
   constexpr IValueT Sbc = B2 | B1; // 0110
-  emitType01(Sbc, OpRd, OpRn, OpSrc1, SetFlags, Cond);
+  emitType01(Sbc, OpRd, OpRn, OpSrc1, SetFlags, Cond, RdIsPcAndSetFlags);
 }
 
 void AssemblerARM32::sdiv(const Operand *OpRd, const Operand *OpRn,
                           const Operand *OpSrc1, CondARM32::Cond Cond) {
   // SDIV - ARM section A8.8.165, encoding A1.
   //   sdiv<c> <Rd>, <Rn>, <Rm>
   //
   // cccc01110001dddd1111mmmm0001nnnn where cccc=Cond, dddd=Rd, nnnn=Rn, and
   // mmmm=Rm.
   IValueT Rd;
@@ skipping 57 matching lines @@
   //
   // cccc0001100snnnnddddiiiiitt0mmmm where cccc=Cond, dddd=Rd, nnnn=Rn,
   // mmmm=Rm, iiiii=shift, tt=ShiftKind,, and s=SetFlags.
   //
   // ORR (register) - ARM Section A8.8.123, encoding A1:
   //   orr{s}<c> <Rd>, <Rn>,  #<RotatedImm8>
   //
   // cccc0001100snnnnddddiiiiiiiiiiii where cccc=Cond, dddd=Rd, nnnn=Rn,
   // s=SetFlags and iiiiiiiiiiii=Src1Value defining RotatedImm8.
   constexpr IValueT Orr = B3 | B2; // i.e. 1100
-  emitType01(Orr, OpRd, OpRn, OpSrc1, SetFlags, Cond);
+  emitType01(Orr, OpRd, OpRn, OpSrc1, SetFlags, Cond, RdIsPcAndSetFlags);
 }
 
 void AssemblerARM32::pop(const Operand *OpRt, CondARM32::Cond Cond) {
   // POP - ARM section A8.8.132, encoding A2:
   //   pop<c> {Rt}
   //
   // cccc010010011101dddd000000000100 where dddd=Rt and cccc=Cond.
   IValueT Rt;
   if (decodeOperand(OpRt, Rt) != DecodedAsRegister)
     return setNeedsTextFixup();
@@ skipping 133 matching lines @@
   // mmmm=Rm, iiiiii=shift, tt=ShiftKind, and s=SetFlags.
   //
   // Sub (Immediate) - ARM section A8.8.222, encoding A1:
   //    sub{s}<c> <Rd>, <Rn>, #<RotatedImm8>
   // Sub (Sp minus immediate) - ARM section A8.*.225, encoding A1:
   //    sub{s}<c> sp, <Rn>, #<RotatedImm8>
   //
   // cccc0010010snnnnddddiiiiiiiiiiii where cccc=Cond, dddd=Rd, nnnn=Rn,
   // s=SetFlags and iiiiiiiiiiii=Src1Value defining RotatedImm8
   constexpr IValueT Sub = B1; // 0010
-  emitType01(Sub, OpRd, OpRn, OpSrc1, SetFlags, Cond);
+  emitType01(Sub, OpRd, OpRn, OpSrc1, SetFlags, Cond, RdIsPcAndSetFlags);
 }
 
 void AssemblerARM32::tst(const Operand *OpRn, const Operand *OpSrc1,
                          CondARM32::Cond Cond) {
   // TST (register) - ARM section A8.8.241, encoding A1:
   //   tst<c> <Rn>, <Rm>(, <shift>}
   //
   // cccc00010001nnnn0000iiiiitt0mmmm where cccc=Cond, nnnn=Rn, mmmm=Rm,
   // iiiii=Shift, and tt=ShiftKind.
   //
@@ skipping 63 matching lines @@
     // rr defined (RotationValue) rotate.
     constexpr IValueT Opcode = B26 | B25 | B23 | B22 | B21 | B20;
     emitUxt(Cond, Opcode, Rd, Rn, Rm, Rotation);
     return;
   }
   }
 }
 
 } // end of namespace ARM32
 } // end of namespace Ice