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| 1 // Copyright (c) 2013, the Dart project authors. Please see the AUTHORS file | 1 // Copyright (c) 2013, the Dart project authors. Please see the AUTHORS file |
| 2 // for details. All rights reserved. Use of this source code is governed by a | 2 // for details. All rights reserved. Use of this source code is governed by a |
| 3 // BSD-style license that can be found in the LICENSE file. | 3 // BSD-style license that can be found in the LICENSE file. |
| 4 // | 4 // |
| 5 // This is forked from Dart revision df52deea9f25690eb8b66c5995da92b70f7ac1fe | 5 // This is forked from Dart revision df52deea9f25690eb8b66c5995da92b70f7ac1fe |
| 6 // Please update the (git) revision if we merge changes from Dart. | 6 // Please update the (git) revision if we merge changes from Dart. |
| 7 // https://code.google.com/p/dart/wiki/GettingTheSource | 7 // https://code.google.com/p/dart/wiki/GettingTheSource |
| 8 | 8 |
| 9 #include "vm/globals.h" // NOLINT | 9 #include "vm/globals.h" // NOLINT |
| 10 #if defined(TARGET_ARCH_ARM) | 10 #if defined(TARGET_ARCH_ARM) |
| (...skipping 2578 matching lines...) Expand 10 before | Expand all | Expand 10 after Loading... |
| 2589 ldm(IA_W, SP, regs, cond); | 2589 ldm(IA_W, SP, regs, cond); |
| 2590 } | 2590 } |
| 2591 #endif | 2591 #endif |
| 2592 | 2592 |
| 2593 void Assembler::MoveRegister(Register rd, Register rm, Condition cond) { | 2593 void Assembler::MoveRegister(Register rd, Register rm, Condition cond) { |
| 2594 if (rd != rm) { | 2594 if (rd != rm) { |
| 2595 mov(rd, Operand(rm), cond); | 2595 mov(rd, Operand(rm), cond); |
| 2596 } | 2596 } |
| 2597 } | 2597 } |
| 2598 | 2598 |
| 2599 | 2599 #if 0 |
| 2600 // Moved to ARM32::AssemblerARM32::lsl() |
| 2600 void Assembler::Lsl(Register rd, Register rm, const Operand& shift_imm, | 2601 void Assembler::Lsl(Register rd, Register rm, const Operand& shift_imm, |
| 2601 Condition cond) { | 2602 Condition cond) { |
| 2602 ASSERT(shift_imm.type() == 1); | 2603 ASSERT(shift_imm.type() == 1); |
| 2603 ASSERT(shift_imm.encoding() != 0); // Do not use Lsl if no shift is wanted. | 2604 ASSERT(shift_imm.encoding() != 0); // Do not use Lsl if no shift is wanted. |
| 2604 mov(rd, Operand(rm, LSL, shift_imm.encoding()), cond); | 2605 mov(rd, Operand(rm, LSL, shift_imm.encoding()), cond); |
| 2605 } | 2606 } |
| 2606 | 2607 |
| 2607 | 2608 // Moved to ARM32::AssemblerARM32::lsl() |
| 2608 void Assembler::Lsl(Register rd, Register rm, Register rs, Condition cond) { | 2609 void Assembler::Lsl(Register rd, Register rm, Register rs, Condition cond) { |
| 2609 mov(rd, Operand(rm, LSL, rs), cond); | 2610 mov(rd, Operand(rm, LSL, rs), cond); |
| 2610 } | 2611 } |
| 2612 #endif |
| 2611 | 2613 |
| 2612 | 2614 |
| 2613 void Assembler::Lsr(Register rd, Register rm, const Operand& shift_imm, | 2615 void Assembler::Lsr(Register rd, Register rm, const Operand& shift_imm, |
| 2614 Condition cond) { | 2616 Condition cond) { |
| 2615 ASSERT(shift_imm.type() == 1); | 2617 ASSERT(shift_imm.type() == 1); |
| 2616 uint32_t shift = shift_imm.encoding(); | 2618 uint32_t shift = shift_imm.encoding(); |
| 2617 ASSERT(shift != 0); // Do not use Lsr if no shift is wanted. | 2619 ASSERT(shift != 0); // Do not use Lsr if no shift is wanted. |
| 2618 if (shift == 32) { | 2620 if (shift == 32) { |
| 2619 shift = 0; // Comply to UAL syntax. | 2621 shift = 0; // Comply to UAL syntax. |
| 2620 } | 2622 } |
| (...skipping 1070 matching lines...) Expand 10 before | Expand all | Expand 10 after Loading... |
| 3691 | 3693 |
| 3692 | 3694 |
| 3693 const char* Assembler::FpuRegisterName(FpuRegister reg) { | 3695 const char* Assembler::FpuRegisterName(FpuRegister reg) { |
| 3694 ASSERT((0 <= reg) && (reg < kNumberOfFpuRegisters)); | 3696 ASSERT((0 <= reg) && (reg < kNumberOfFpuRegisters)); |
| 3695 return fpu_reg_names[reg]; | 3697 return fpu_reg_names[reg]; |
| 3696 } | 3698 } |
| 3697 | 3699 |
| 3698 } // namespace dart | 3700 } // namespace dart |
| 3699 | 3701 |
| 3700 #endif // defined TARGET_ARCH_ARM | 3702 #endif // defined TARGET_ARCH_ARM |
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