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1 // Copyright 2014 the V8 project authors. All rights reserved. | 1 // Copyright 2014 the V8 project authors. All rights reserved. |
2 // Use of this source code is governed by a BSD-style license that can be | 2 // Use of this source code is governed by a BSD-style license that can be |
3 // found in the LICENSE file. | 3 // found in the LICENSE file. |
4 | 4 |
5 #ifndef V8_COMPILER_PPC_INSTRUCTION_CODES_PPC_H_ | 5 #ifndef V8_COMPILER_PPC_INSTRUCTION_CODES_PPC_H_ |
6 #define V8_COMPILER_PPC_INSTRUCTION_CODES_PPC_H_ | 6 #define V8_COMPILER_PPC_INSTRUCTION_CODES_PPC_H_ |
7 | 7 |
8 namespace v8 { | 8 namespace v8 { |
9 namespace internal { | 9 namespace internal { |
10 namespace compiler { | 10 namespace compiler { |
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80 V(PPC_Int64ToInt32) \ | 80 V(PPC_Int64ToInt32) \ |
81 V(PPC_Int64ToFloat32) \ | 81 V(PPC_Int64ToFloat32) \ |
82 V(PPC_Int64ToDouble) \ | 82 V(PPC_Int64ToDouble) \ |
83 V(PPC_Uint64ToFloat32) \ | 83 V(PPC_Uint64ToFloat32) \ |
84 V(PPC_Uint64ToDouble) \ | 84 V(PPC_Uint64ToDouble) \ |
85 V(PPC_Int32ToDouble) \ | 85 V(PPC_Int32ToDouble) \ |
86 V(PPC_Uint32ToDouble) \ | 86 V(PPC_Uint32ToDouble) \ |
87 V(PPC_Float32ToDouble) \ | 87 V(PPC_Float32ToDouble) \ |
88 V(PPC_DoubleToInt32) \ | 88 V(PPC_DoubleToInt32) \ |
89 V(PPC_DoubleToUint32) \ | 89 V(PPC_DoubleToUint32) \ |
| 90 V(PPC_DoubleToInt64) \ |
90 V(PPC_DoubleToFloat32) \ | 91 V(PPC_DoubleToFloat32) \ |
91 V(PPC_DoubleExtractLowWord32) \ | 92 V(PPC_DoubleExtractLowWord32) \ |
92 V(PPC_DoubleExtractHighWord32) \ | 93 V(PPC_DoubleExtractHighWord32) \ |
93 V(PPC_DoubleInsertLowWord32) \ | 94 V(PPC_DoubleInsertLowWord32) \ |
94 V(PPC_DoubleInsertHighWord32) \ | 95 V(PPC_DoubleInsertHighWord32) \ |
95 V(PPC_DoubleConstruct) \ | 96 V(PPC_DoubleConstruct) \ |
96 V(PPC_BitcastInt32ToFloat32) \ | 97 V(PPC_BitcastInt32ToFloat32) \ |
97 V(PPC_BitcastFloat32ToInt32) \ | 98 V(PPC_BitcastFloat32ToInt32) \ |
98 V(PPC_BitcastInt64ToDouble) \ | 99 V(PPC_BitcastInt64ToDouble) \ |
99 V(PPC_BitcastDoubleToInt64) \ | 100 V(PPC_BitcastDoubleToInt64) \ |
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128 // MRR = [register + register] | 129 // MRR = [register + register] |
129 #define TARGET_ADDRESSING_MODE_LIST(V) \ | 130 #define TARGET_ADDRESSING_MODE_LIST(V) \ |
130 V(MRI) /* [%r0 + K] */ \ | 131 V(MRI) /* [%r0 + K] */ \ |
131 V(MRR) /* [%r0 + %r1] */ | 132 V(MRR) /* [%r0 + %r1] */ |
132 | 133 |
133 } // namespace compiler | 134 } // namespace compiler |
134 } // namespace internal | 135 } // namespace internal |
135 } // namespace v8 | 136 } // namespace v8 |
136 | 137 |
137 #endif // V8_COMPILER_PPC_INSTRUCTION_CODES_PPC_H_ | 138 #endif // V8_COMPILER_PPC_INSTRUCTION_CODES_PPC_H_ |
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