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Side by Side Diff: src/IceTargetLoweringMIPS32.cpp

Issue 1455033005: Subzero. Adds a pass for target-specific helper call generation. (Closed) Base URL: https://chromium.googlesource.com/native_client/pnacl-subzero.git@master
Patch Set: Created 5 years, 1 month ago
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1 //===- subzero/src/IceTargetLoweringMIPS32.cpp - MIPS32 lowering ----------===// 1 //===- subzero/src/IceTargetLoweringMIPS32.cpp - MIPS32 lowering ----------===//
2 // 2 //
3 // The Subzero Code Generator 3 // The Subzero Code Generator
4 // 4 //
5 // This file is distributed under the University of Illinois Open Source 5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details. 6 // License. See LICENSE.TXT for details.
7 // 7 //
8 //===----------------------------------------------------------------------===// 8 //===----------------------------------------------------------------------===//
9 /// 9 ///
10 /// \file 10 /// \file
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84 TypeToRegisterSet[IceType_v8i16] = VectorRegisters; 84 TypeToRegisterSet[IceType_v8i16] = VectorRegisters;
85 TypeToRegisterSet[IceType_v4i32] = VectorRegisters; 85 TypeToRegisterSet[IceType_v4i32] = VectorRegisters;
86 TypeToRegisterSet[IceType_v4f32] = VectorRegisters; 86 TypeToRegisterSet[IceType_v4f32] = VectorRegisters;
87 } 87 }
88 88
89 void TargetMIPS32::translateO2() { 89 void TargetMIPS32::translateO2() {
90 TimerMarker T(TimerStack::TT_O2, Func); 90 TimerMarker T(TimerStack::TT_O2, Func);
91 91
92 // TODO(stichnot): share passes with X86? 92 // TODO(stichnot): share passes with X86?
93 // https://code.google.com/p/nativeclient/issues/detail?id=4094 93 // https://code.google.com/p/nativeclient/issues/detail?id=4094
94 genTargetHelperCalls();
94 95
95 // Merge Alloca instructions, and lay out the stack. 96 // Merge Alloca instructions, and lay out the stack.
96 static constexpr bool SortAndCombineAllocas = true; 97 static constexpr bool SortAndCombineAllocas = true;
97 Func->processAllocas(SortAndCombineAllocas); 98 Func->processAllocas(SortAndCombineAllocas);
98 Func->dump("After Alloca processing"); 99 Func->dump("After Alloca processing");
99 100
100 if (!Ctx->getFlags().getPhiEdgeSplit()) { 101 if (!Ctx->getFlags().getPhiEdgeSplit()) {
101 // Lower Phi instructions. 102 // Lower Phi instructions.
102 Func->placePhiLoads(); 103 Func->placePhiLoads();
103 if (Func->hasError()) 104 if (Func->hasError())
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184 // Nop insertion 185 // Nop insertion
185 if (Ctx->getFlags().shouldDoNopInsertion()) { 186 if (Ctx->getFlags().shouldDoNopInsertion()) {
186 Func->doNopInsertion(); 187 Func->doNopInsertion();
187 } 188 }
188 } 189 }
189 190
190 void TargetMIPS32::translateOm1() { 191 void TargetMIPS32::translateOm1() {
191 TimerMarker T(TimerStack::TT_Om1, Func); 192 TimerMarker T(TimerStack::TT_Om1, Func);
192 193
193 // TODO: share passes with X86? 194 // TODO: share passes with X86?
195 genTargetHelperCalls();
194 196
195 // Do not merge Alloca instructions, and lay out the stack. 197 // Do not merge Alloca instructions, and lay out the stack.
196 static constexpr bool SortAndCombineAllocas = false; 198 static constexpr bool SortAndCombineAllocas = false;
197 Func->processAllocas(SortAndCombineAllocas); 199 Func->processAllocas(SortAndCombineAllocas);
198 Func->dump("After Alloca processing"); 200 Func->dump("After Alloca processing");
199 201
200 Func->placePhiLoads(); 202 Func->placePhiLoads();
201 if (Func->hasError()) 203 if (Func->hasError())
202 return; 204 return;
203 Func->placePhiStores(); 205 Func->placePhiStores();
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1072 Ostream &Str = Ctx->getStrEmit(); 1074 Ostream &Str = Ctx->getStrEmit();
1073 Str << "\t.set\tnomicromips\n"; 1075 Str << "\t.set\tnomicromips\n";
1074 Str << "\t.set\tnomips16\n"; 1076 Str << "\t.set\tnomips16\n";
1075 } 1077 }
1076 1078
1077 llvm::SmallBitVector TargetMIPS32::TypeToRegisterSet[IceType_NUM]; 1079 llvm::SmallBitVector TargetMIPS32::TypeToRegisterSet[IceType_NUM];
1078 llvm::SmallBitVector TargetMIPS32::RegisterAliases[RegMIPS32::Reg_NUM]; 1080 llvm::SmallBitVector TargetMIPS32::RegisterAliases[RegMIPS32::Reg_NUM];
1079 llvm::SmallBitVector TargetMIPS32::ScratchRegs; 1081 llvm::SmallBitVector TargetMIPS32::ScratchRegs;
1080 1082
1081 } // end of namespace Ice 1083 } // end of namespace Ice
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