OLD | NEW |
1 // Copyright 2012 the V8 project authors. All rights reserved. | 1 // Copyright 2012 the V8 project authors. All rights reserved. |
2 // Use of this source code is governed by a BSD-style license that can be | 2 // Use of this source code is governed by a BSD-style license that can be |
3 // found in the LICENSE file. | 3 // found in the LICENSE file. |
4 | 4 |
5 #include <limits.h> // For LONG_MIN, LONG_MAX. | 5 #include <limits.h> // For LONG_MIN, LONG_MAX. |
6 | 6 |
7 #if V8_TARGET_ARCH_MIPS64 | 7 #if V8_TARGET_ARCH_MIPS64 |
8 | 8 |
9 #include "src/base/division-by-constant.h" | 9 #include "src/base/division-by-constant.h" |
10 #include "src/bootstrapper.h" | 10 #include "src/bootstrapper.h" |
(...skipping 1485 matching lines...) Expand 10 before | Expand all | Expand 10 after Loading... |
1496 | 1496 |
1497 void MacroAssembler::Cvt_d_uw(FPURegister fd, FPURegister fs) { | 1497 void MacroAssembler::Cvt_d_uw(FPURegister fd, FPURegister fs) { |
1498 // Move the data from fs to t8. | 1498 // Move the data from fs to t8. |
1499 mfc1(t8, fs); | 1499 mfc1(t8, fs); |
1500 Cvt_d_uw(fd, t8); | 1500 Cvt_d_uw(fd, t8); |
1501 } | 1501 } |
1502 | 1502 |
1503 | 1503 |
1504 void MacroAssembler::Cvt_d_uw(FPURegister fd, Register rs) { | 1504 void MacroAssembler::Cvt_d_uw(FPURegister fd, Register rs) { |
1505 // Convert rs to a FP value in fd. | 1505 // Convert rs to a FP value in fd. |
1506 DCHECK(!fd.is(scratch)); | |
1507 DCHECK(!rs.is(t9)); | 1506 DCHECK(!rs.is(t9)); |
1508 DCHECK(!rs.is(at)); | 1507 DCHECK(!rs.is(at)); |
1509 | 1508 |
1510 // Zero extend int32 in rs. | 1509 // Zero extend int32 in rs. |
1511 Dext(t9, rs, 0, 32); | 1510 Dext(t9, rs, 0, 32); |
1512 dmtc1(t9, fd); | 1511 dmtc1(t9, fd); |
1513 cvt_d_l(fd, fd); | 1512 cvt_d_l(fd, fd); |
1514 } | 1513 } |
1515 | 1514 |
1516 | 1515 |
(...skipping 4686 matching lines...) Expand 10 before | Expand all | Expand 10 after Loading... |
6203 if (mag.shift > 0) sra(result, result, mag.shift); | 6202 if (mag.shift > 0) sra(result, result, mag.shift); |
6204 srl(at, dividend, 31); | 6203 srl(at, dividend, 31); |
6205 Addu(result, result, Operand(at)); | 6204 Addu(result, result, Operand(at)); |
6206 } | 6205 } |
6207 | 6206 |
6208 | 6207 |
6209 } // namespace internal | 6208 } // namespace internal |
6210 } // namespace v8 | 6209 } // namespace v8 |
6211 | 6210 |
6212 #endif // V8_TARGET_ARCH_MIPS64 | 6211 #endif // V8_TARGET_ARCH_MIPS64 |
OLD | NEW |