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Issue 1453373002: ​MIPS: Improve Cvt_d_uw on mips32. (Closed) Base URL: https://chromium.googlesource.com/v8/v8.git@master
Patch Set: Further improvements Created 5 years, 1 month ago
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1 1
2 // Copyright 2012 the V8 project authors. All rights reserved. 2 // Copyright 2012 the V8 project authors. All rights reserved.
3 // Use of this source code is governed by a BSD-style license that can be 3 // Use of this source code is governed by a BSD-style license that can be
4 // found in the LICENSE file. 4 // found in the LICENSE file.
5 5
6 #include <limits.h> // For LONG_MIN, LONG_MAX. 6 #include <limits.h> // For LONG_MIN, LONG_MAX.
7 7
8 #if V8_TARGET_ARCH_MIPS 8 #if V8_TARGET_ARCH_MIPS
9 9
10 #include "src/base/bits.h" 10 #include "src/base/bits.h"
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1260 and_(t8, rs, at); 1260 and_(t8, rs, at);
1261 sll(t8, t8, pos); 1261 sll(t8, t8, pos);
1262 sll(at, at, pos); 1262 sll(at, at, pos);
1263 nor(at, at, zero_reg); 1263 nor(at, at, zero_reg);
1264 and_(at, rt, at); 1264 and_(at, rt, at);
1265 or_(rt, t8, at); 1265 or_(rt, t8, at);
1266 } 1266 }
1267 } 1267 }
1268 1268
1269 1269
1270 void MacroAssembler::Cvt_d_uw(FPURegister fd, 1270 void MacroAssembler::Cvt_d_uw(FPURegister fd, Register rs,
1271 FPURegister fs,
1272 FPURegister scratch) { 1271 FPURegister scratch) {
1273 // Move the data from fs to t8. 1272 // In FP64Mode we do convertion from long.
1274 mfc1(t8, fs); 1273 if (IsFp64Mode()) {
1275 Cvt_d_uw(fd, t8, scratch); 1274 mtc1(rs, scratch);
1275 cvt_d_l(fd, scratch);
1276 } else {
1277 // Convert rs to a FP value in fd.
1278 DCHECK(!fd.is(scratch));
1279 DCHECK(!rs.is(t9));
ivica.bogosavljevic 2015/11/23 08:56:45 On one hand, I wished you weren't using register t
paul.l... 2015/11/23 15:57:40 Well, I was going to point out that t9 (and t8) ar
1280 DCHECK(!rs.is(at));
1281
1282 Label msb_clear, conversion_done;
1283 // For a value which is < 2^31, regard it as a signed positve word.
1284 Branch(&msb_clear, ge, rs, Operand(zero_reg), USE_DELAY_SLOT);
1285 mtc1(rs, fd);
1286
1287 lui(at, 0x41F0); // FP value: 2^32.
1288
1289 // For unsigned inputs > 2^31, we convert to double as a signed int32,
1290 // then add 2^32 to move it back to unsigned value in range 2^31..2^31-1.
1291 mtc1(zero_reg, scratch);
1292 Mthc1(at, scratch);
1293
1294 cvt_d_w(fd, fd);
1295
1296 Branch(USE_DELAY_SLOT, &conversion_done);
1297 add_d(fd, fd, scratch);
1298
1299 bind(&msb_clear);
1300 cvt_d_w(fd, fd);
1301
1302 bind(&conversion_done);
1303 }
1276 } 1304 }
1277 1305
1278 1306
1279 void MacroAssembler::Cvt_d_uw(FPURegister fd,
1280 Register rs,
1281 FPURegister scratch) {
1282 // Convert rs to a FP value in fd (and fd + 1).
1283 // We do this by converting rs minus the MSB to avoid sign conversion,
1284 // then adding 2^31 to the result (if needed).
1285
1286 DCHECK(!fd.is(scratch));
1287 DCHECK(!rs.is(t9));
1288 DCHECK(!rs.is(at));
1289
1290 // Save rs's MSB to t9.
1291 Ext(t9, rs, 31, 1);
1292 // Remove rs's MSB.
1293 Ext(at, rs, 0, 31);
1294 // Move the result to fd.
1295 mtc1(at, fd);
1296
1297 // Convert fd to a real FP value.
1298 cvt_d_w(fd, fd);
1299
1300 Label conversion_done;
1301
1302 // If rs's MSB was 0, it's done.
1303 // Otherwise we need to add that to the FP register.
1304 Branch(&conversion_done, eq, t9, Operand(zero_reg));
1305
1306 // Load 2^31 into f20 as its float representation.
1307 li(at, 0x41E00000);
1308 mtc1(zero_reg, scratch);
1309 Mthc1(at, scratch);
1310 // Add it to fd.
1311 add_d(fd, fd, scratch);
1312
1313 bind(&conversion_done);
1314 }
1315
1316
1317 void MacroAssembler::Trunc_uw_d(FPURegister fd, 1307 void MacroAssembler::Trunc_uw_d(FPURegister fd,
1318 FPURegister fs, 1308 FPURegister fs,
1319 FPURegister scratch) { 1309 FPURegister scratch) {
1320 Trunc_uw_d(fs, t8, scratch); 1310 Trunc_uw_d(fs, t8, scratch);
1321 mtc1(t8, fd); 1311 mtc1(t8, fd);
1322 } 1312 }
1323 1313
1324 1314
1325 void MacroAssembler::Trunc_w_d(FPURegister fd, FPURegister fs) { 1315 void MacroAssembler::Trunc_w_d(FPURegister fd, FPURegister fs) {
1326 if (IsMipsArchVariant(kLoongson) && fd.is(fs)) { 1316 if (IsMipsArchVariant(kLoongson) && fd.is(fs)) {
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5845 if (mag.shift > 0) sra(result, result, mag.shift); 5835 if (mag.shift > 0) sra(result, result, mag.shift);
5846 srl(at, dividend, 31); 5836 srl(at, dividend, 31);
5847 Addu(result, result, Operand(at)); 5837 Addu(result, result, Operand(at));
5848 } 5838 }
5849 5839
5850 5840
5851 } // namespace internal 5841 } // namespace internal
5852 } // namespace v8 5842 } // namespace v8
5853 5843
5854 #endif // V8_TARGET_ARCH_MIPS 5844 #endif // V8_TARGET_ARCH_MIPS
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