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2 // Copyright 2012 the V8 project authors. All rights reserved. | 2 // Copyright 2012 the V8 project authors. All rights reserved. |
3 // Use of this source code is governed by a BSD-style license that can be | 3 // Use of this source code is governed by a BSD-style license that can be |
4 // found in the LICENSE file. | 4 // found in the LICENSE file. |
5 | 5 |
6 #include <limits.h> // For LONG_MIN, LONG_MAX. | 6 #include <limits.h> // For LONG_MIN, LONG_MAX. |
7 | 7 |
8 #if V8_TARGET_ARCH_MIPS | 8 #if V8_TARGET_ARCH_MIPS |
9 | 9 |
10 #include "src/base/bits.h" | 10 #include "src/base/bits.h" |
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1263 nor(at, at, zero_reg); | 1263 nor(at, at, zero_reg); |
1264 and_(at, rt, at); | 1264 and_(at, rt, at); |
1265 or_(rt, t8, at); | 1265 or_(rt, t8, at); |
1266 } | 1266 } |
1267 } | 1267 } |
1268 | 1268 |
1269 | 1269 |
1270 void MacroAssembler::Cvt_d_uw(FPURegister fd, | 1270 void MacroAssembler::Cvt_d_uw(FPURegister fd, |
1271 FPURegister fs, | 1271 FPURegister fs, |
1272 FPURegister scratch) { | 1272 FPURegister scratch) { |
1273 // Move the data from fs to t8. | 1273 if (IsFp64Mode()) { |
1274 mfc1(t8, fs); | 1274 // On FP64Mode we can simple do convertion from long. |
paul.l...
2015/11/19 01:23:38
Nits: fix spelling and word order in this sentence
Alan Li
2015/11/20 17:57:55
Done.
| |
1275 Cvt_d_uw(fd, t8, scratch); | 1275 cvt_d_l(fd, fs); |
1276 } else { | |
1277 mfc1(t8, fs); | |
1278 Cvt_d_uw(fd, t8, scratch, fs); | |
1279 } | |
1276 } | 1280 } |
1277 | 1281 |
1278 | 1282 |
1279 void MacroAssembler::Cvt_d_uw(FPURegister fd, | 1283 void MacroAssembler::Cvt_d_uw(FPURegister fd, Register rs, FPURegister scratch, |
1280 Register rs, | 1284 FPURegister fs) { |
1281 FPURegister scratch) { | |
1282 // Convert rs to a FP value in fd (and fd + 1). | 1285 // Convert rs to a FP value in fd (and fd + 1). |
paul.l...
2015/11/19 01:23:38
Remove the '(and fd + 1); from the comment. While
Alan Li
2015/11/20 17:57:55
Done.
| |
1283 // We do this by converting rs minus the MSB to avoid sign conversion, | |
1284 // then adding 2^31 to the result (if needed). | |
1285 | |
1286 DCHECK(!fd.is(scratch)); | 1286 DCHECK(!fd.is(scratch)); |
1287 DCHECK(!rs.is(t9)); | 1287 DCHECK(!rs.is(t9)); |
1288 DCHECK(!rs.is(at)); | 1288 DCHECK(!rs.is(at)); |
1289 | 1289 |
1290 // Save rs's MSB to t9. | 1290 Label msb_clear, conversion_done; |
1291 Ext(t9, rs, 31, 1); | 1291 // For a value which is < 2^31, regard it as a signed positve word. |
1292 // Remove rs's MSB. | 1292 Branch(&msb_clear, ge, rs, Operand(zero_reg), USE_DELAY_SLOT); |
1293 Ext(at, rs, 0, 31); | 1293 lui(at, 0x41F0); // FP value: 2^32, in delay slot. |
1294 // Move the result to fd. | |
1295 mtc1(at, fd); | |
1296 | 1294 |
1297 // Convert fd to a real FP value. | 1295 // For unsigned word A which is greater than 2^31, consider this fact: |
1298 cvt_d_w(fd, fd); | 1296 // A = 2^32 + reinterpret_cast<int32>(A) |
1299 | 1297 // Thus we can first regard A as signed word and cast it into double, |
1300 Label conversion_done; | 1298 // then add 2^32 on the result to complete the casting. |
paul.l...
2015/11/19 01:23:38
Comment is too wordy, and strangely worded, we don
Alan Li
2015/11/20 17:57:55
Done.
| |
1301 | |
1302 // If rs's MSB was 0, it's done. | |
1303 // Otherwise we need to add that to the FP register. | |
1304 Branch(&conversion_done, eq, t9, Operand(zero_reg)); | |
1305 | |
1306 // Load 2^31 into f20 as its float representation. | |
1307 li(at, 0x41E00000); | |
1308 mtc1(zero_reg, scratch); | 1299 mtc1(zero_reg, scratch); |
1309 Mthc1(at, scratch); | 1300 Mthc1(at, scratch); |
1310 // Add it to fd. | 1301 |
1302 if (fs.is(no_freg)) { | |
1303 mtc1(rs, fd); | |
1304 cvt_d_w(fd, fd); | |
1305 } else { | |
1306 cvt_d_w(fd, fs); | |
1307 } | |
1308 | |
1309 Branch(USE_DELAY_SLOT, &conversion_done); | |
1311 add_d(fd, fd, scratch); | 1310 add_d(fd, fd, scratch); |
1312 | 1311 |
1312 bind(&msb_clear); | |
1313 if (fs.is(no_freg)) { | |
1314 mtc1(rs, fd); | |
1315 cvt_d_w(fd, fd); | |
1316 } else { | |
1317 cvt_d_w(fd, fs); | |
1318 } | |
1319 | |
1313 bind(&conversion_done); | 1320 bind(&conversion_done); |
1314 } | 1321 } |
1315 | 1322 |
1316 | 1323 |
1317 void MacroAssembler::Trunc_uw_d(FPURegister fd, | 1324 void MacroAssembler::Trunc_uw_d(FPURegister fd, |
1318 FPURegister fs, | 1325 FPURegister fs, |
1319 FPURegister scratch) { | 1326 FPURegister scratch) { |
1320 Trunc_uw_d(fs, t8, scratch); | 1327 Trunc_uw_d(fs, t8, scratch); |
1321 mtc1(t8, fd); | 1328 mtc1(t8, fd); |
1322 } | 1329 } |
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5854 if (mag.shift > 0) sra(result, result, mag.shift); | 5861 if (mag.shift > 0) sra(result, result, mag.shift); |
5855 srl(at, dividend, 31); | 5862 srl(at, dividend, 31); |
5856 Addu(result, result, Operand(at)); | 5863 Addu(result, result, Operand(at)); |
5857 } | 5864 } |
5858 | 5865 |
5859 | 5866 |
5860 } // namespace internal | 5867 } // namespace internal |
5861 } // namespace v8 | 5868 } // namespace v8 |
5862 | 5869 |
5863 #endif // V8_TARGET_ARCH_MIPS | 5870 #endif // V8_TARGET_ARCH_MIPS |
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