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Side by Side Diff: src/mips/macro-assembler-mips.h

Issue 1453373002: ​MIPS: Improve Cvt_d_uw on mips32. (Closed) Base URL: https://chromium.googlesource.com/v8/v8.git@master
Patch Set: fix compilation errors. Created 5 years ago
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1 // Copyright 2012 the V8 project authors. All rights reserved. 1 // Copyright 2012 the V8 project authors. All rights reserved.
2 // Use of this source code is governed by a BSD-style license that can be 2 // Use of this source code is governed by a BSD-style license that can be
3 // found in the LICENSE file. 3 // found in the LICENSE file.
4 4
5 #ifndef V8_MIPS_MACRO_ASSEMBLER_MIPS_H_ 5 #ifndef V8_MIPS_MACRO_ASSEMBLER_MIPS_H_
6 #define V8_MIPS_MACRO_ASSEMBLER_MIPS_H_ 6 #define V8_MIPS_MACRO_ASSEMBLER_MIPS_H_
7 7
8 #include "src/assembler.h" 8 #include "src/assembler.h"
9 #include "src/globals.h" 9 #include "src/globals.h"
10 #include "src/mips/assembler-mips.h" 10 #include "src/mips/assembler-mips.h"
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768 void LoadFromSafepointRegisterSlot(Register dst, Register src); 768 void LoadFromSafepointRegisterSlot(Register dst, Register src);
769 769
770 // MIPS32 R2 instruction macro. 770 // MIPS32 R2 instruction macro.
771 void Ins(Register rt, Register rs, uint16_t pos, uint16_t size); 771 void Ins(Register rt, Register rs, uint16_t pos, uint16_t size);
772 void Ext(Register rt, Register rs, uint16_t pos, uint16_t size); 772 void Ext(Register rt, Register rs, uint16_t pos, uint16_t size);
773 773
774 // --------------------------------------------------------------------------- 774 // ---------------------------------------------------------------------------
775 // FPU macros. These do not handle special cases like NaN or +- inf. 775 // FPU macros. These do not handle special cases like NaN or +- inf.
776 776
777 // Convert unsigned word to double. 777 // Convert unsigned word to double.
778 void Cvt_d_uw(FPURegister fd, FPURegister fs, FPURegister scratch);
779 void Cvt_d_uw(FPURegister fd, Register rs, FPURegister scratch); 778 void Cvt_d_uw(FPURegister fd, Register rs, FPURegister scratch);
780 779
781 // Convert double to unsigned word. 780 // Convert double to unsigned word.
782 void Trunc_uw_d(FPURegister fd, FPURegister fs, FPURegister scratch); 781 void Trunc_uw_d(FPURegister fd, FPURegister fs, FPURegister scratch);
783 void Trunc_uw_d(FPURegister fd, Register rs, FPURegister scratch); 782 void Trunc_uw_d(FPURegister fd, Register rs, FPURegister scratch);
784 783
785 void Trunc_w_d(FPURegister fd, FPURegister fs); 784 void Trunc_w_d(FPURegister fd, FPURegister fs);
786 void Round_w_d(FPURegister fd, FPURegister fs); 785 void Round_w_d(FPURegister fd, FPURegister fs);
787 void Floor_w_d(FPURegister fd, FPURegister fs); 786 void Floor_w_d(FPURegister fd, FPURegister fs);
788 void Ceil_w_d(FPURegister fd, FPURegister fs); 787 void Ceil_w_d(FPURegister fd, FPURegister fs);
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1754 #define __FILE_LINE__ __FILE__ ":" CODE_COVERAGE_TOSTRING(__LINE__) 1753 #define __FILE_LINE__ __FILE__ ":" CODE_COVERAGE_TOSTRING(__LINE__)
1755 #define ACCESS_MASM(masm) masm->stop(__FILE_LINE__); masm-> 1754 #define ACCESS_MASM(masm) masm->stop(__FILE_LINE__); masm->
1756 #else 1755 #else
1757 #define ACCESS_MASM(masm) masm-> 1756 #define ACCESS_MASM(masm) masm->
1758 #endif 1757 #endif
1759 1758
1760 } // namespace internal 1759 } // namespace internal
1761 } // namespace v8 1760 } // namespace v8
1762 1761
1763 #endif // V8_MIPS_MACRO_ASSEMBLER_MIPS_H_ 1762 #endif // V8_MIPS_MACRO_ASSEMBLER_MIPS_H_
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