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Issue 1453373002: ​MIPS: Improve Cvt_d_uw on mips32. (Closed) Base URL: https://chromium.googlesource.com/v8/v8.git@master
Patch Set: fix compilation errors. Created 5 years ago
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1 1
2 // Copyright 2012 the V8 project authors. All rights reserved. 2 // Copyright 2012 the V8 project authors. All rights reserved.
3 // Use of this source code is governed by a BSD-style license that can be 3 // Use of this source code is governed by a BSD-style license that can be
4 // found in the LICENSE file. 4 // found in the LICENSE file.
5 5
6 #include <limits.h> // For LONG_MIN, LONG_MAX. 6 #include <limits.h> // For LONG_MIN, LONG_MAX.
7 7
8 #if V8_TARGET_ARCH_MIPS 8 #if V8_TARGET_ARCH_MIPS
9 9
10 #include "src/base/bits.h" 10 #include "src/base/bits.h"
(...skipping 1247 matching lines...) Expand 10 before | Expand all | Expand 10 after
1258 and_(t8, rs, at); 1258 and_(t8, rs, at);
1259 sll(t8, t8, pos); 1259 sll(t8, t8, pos);
1260 sll(at, at, pos); 1260 sll(at, at, pos);
1261 nor(at, at, zero_reg); 1261 nor(at, at, zero_reg);
1262 and_(at, rt, at); 1262 and_(at, rt, at);
1263 or_(rt, t8, at); 1263 or_(rt, t8, at);
1264 } 1264 }
1265 } 1265 }
1266 1266
1267 1267
1268 void MacroAssembler::Cvt_d_uw(FPURegister fd, 1268 void MacroAssembler::Cvt_d_uw(FPURegister fd, Register rs,
1269 FPURegister fs,
1270 FPURegister scratch) { 1269 FPURegister scratch) {
1271 // Move the data from fs to t8. 1270 // In FP64Mode we do convertion from long.
1272 mfc1(t8, fs); 1271 if (IsFp64Mode()) {
1273 Cvt_d_uw(fd, t8, scratch); 1272 mtc1(rs, scratch);
1273 cvt_d_l(fd, scratch);
1274 } else {
1275 // Convert rs to a FP value in fd.
1276 DCHECK(!fd.is(scratch));
1277 DCHECK(!rs.is(at));
1278
1279 Label msb_clear, conversion_done;
1280 // For a value which is < 2^31, regard it as a signed positve word.
1281 Branch(&msb_clear, ge, rs, Operand(zero_reg), USE_DELAY_SLOT);
1282 mtc1(rs, fd);
1283
1284 li(at, 0x41F00000); // FP value: 2^32.
1285
1286 // For unsigned inputs > 2^31, we convert to double as a signed int32,
1287 // then add 2^32 to move it back to unsigned value in range 2^31..2^31-1.
1288 mtc1(zero_reg, scratch);
1289 Mthc1(at, scratch);
1290
1291 cvt_d_w(fd, fd);
1292
1293 Branch(USE_DELAY_SLOT, &conversion_done);
1294 add_d(fd, fd, scratch);
1295
1296 bind(&msb_clear);
1297 cvt_d_w(fd, fd);
1298
1299 bind(&conversion_done);
1300 }
1274 } 1301 }
1275 1302
1276 1303
1277 void MacroAssembler::Cvt_d_uw(FPURegister fd,
1278 Register rs,
1279 FPURegister scratch) {
1280 // Convert rs to a FP value in fd (and fd + 1).
1281 // We do this by converting rs minus the MSB to avoid sign conversion,
1282 // then adding 2^31 to the result (if needed).
1283
1284 DCHECK(!fd.is(scratch));
1285 DCHECK(!rs.is(t9));
1286 DCHECK(!rs.is(at));
1287
1288 // Save rs's MSB to t9.
1289 Ext(t9, rs, 31, 1);
1290 // Remove rs's MSB.
1291 Ext(at, rs, 0, 31);
1292 // Move the result to fd.
1293 mtc1(at, fd);
1294
1295 // Convert fd to a real FP value.
1296 cvt_d_w(fd, fd);
1297
1298 Label conversion_done;
1299
1300 // If rs's MSB was 0, it's done.
1301 // Otherwise we need to add that to the FP register.
1302 Branch(&conversion_done, eq, t9, Operand(zero_reg));
1303
1304 // Load 2^31 into f20 as its float representation.
1305 li(at, 0x41E00000);
1306 mtc1(zero_reg, scratch);
1307 Mthc1(at, scratch);
1308 // Add it to fd.
1309 add_d(fd, fd, scratch);
1310
1311 bind(&conversion_done);
1312 }
1313
1314
1315 void MacroAssembler::Trunc_uw_d(FPURegister fd, 1304 void MacroAssembler::Trunc_uw_d(FPURegister fd,
1316 FPURegister fs, 1305 FPURegister fs,
1317 FPURegister scratch) { 1306 FPURegister scratch) {
1318 Trunc_uw_d(fs, t8, scratch); 1307 Trunc_uw_d(fs, t8, scratch);
1319 mtc1(t8, fd); 1308 mtc1(t8, fd);
1320 } 1309 }
1321 1310
1322 1311
1323 void MacroAssembler::Trunc_w_d(FPURegister fd, FPURegister fs) { 1312 void MacroAssembler::Trunc_w_d(FPURegister fd, FPURegister fs) {
1324 if (IsMipsArchVariant(kLoongson) && fd.is(fs)) { 1313 if (IsMipsArchVariant(kLoongson) && fd.is(fs)) {
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5825 if (mag.shift > 0) sra(result, result, mag.shift); 5814 if (mag.shift > 0) sra(result, result, mag.shift);
5826 srl(at, dividend, 31); 5815 srl(at, dividend, 31);
5827 Addu(result, result, Operand(at)); 5816 Addu(result, result, Operand(at));
5828 } 5817 }
5829 5818
5830 5819
5831 } // namespace internal 5820 } // namespace internal
5832 } // namespace v8 5821 } // namespace v8
5833 5822
5834 #endif // V8_TARGET_ARCH_MIPS 5823 #endif // V8_TARGET_ARCH_MIPS
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