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Issue 1453373002: ​MIPS: Improve Cvt_d_uw on mips32. (Closed) Base URL: https://chromium.googlesource.com/v8/v8.git@master
Patch Set: Created 5 years, 1 month ago
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1 1
2 // Copyright 2012 the V8 project authors. All rights reserved. 2 // Copyright 2012 the V8 project authors. All rights reserved.
3 // Use of this source code is governed by a BSD-style license that can be 3 // Use of this source code is governed by a BSD-style license that can be
4 // found in the LICENSE file. 4 // found in the LICENSE file.
5 5
6 #include <limits.h> // For LONG_MIN, LONG_MAX. 6 #include <limits.h> // For LONG_MIN, LONG_MAX.
7 7
8 #if V8_TARGET_ARCH_MIPS 8 #if V8_TARGET_ARCH_MIPS
9 9
10 #include "src/base/bits.h" 10 #include "src/base/bits.h"
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1263 nor(at, at, zero_reg); 1263 nor(at, at, zero_reg);
1264 and_(at, rt, at); 1264 and_(at, rt, at);
1265 or_(rt, t8, at); 1265 or_(rt, t8, at);
1266 } 1266 }
1267 } 1267 }
1268 1268
1269 1269
1270 void MacroAssembler::Cvt_d_uw(FPURegister fd, 1270 void MacroAssembler::Cvt_d_uw(FPURegister fd,
1271 FPURegister fs, 1271 FPURegister fs,
1272 FPURegister scratch) { 1272 FPURegister scratch) {
1273 // Move the data from fs to t8. 1273 if (IsFp64Mode()) {
1274 mfc1(t8, fs); 1274 // on FP64Mode we can simple do convertion from long
paul.l... 2015/11/18 01:49:13 Please start comments with capital letter, and end
Alan Li 2015/11/18 17:07:03 Done.
1275 Cvt_d_uw(fd, t8, scratch); 1275 cvt_d_l(fd, fs);
Alan Li 2015/11/18 02:53:21 On FP64Mode, can we assume that fs.high() is fille
Alan Li 2015/11/18 17:07:03 Acknowledged.
1276 } else {
1277 // Move the data from fs to t8.
paul.l... 2015/11/18 01:49:13 There is no need for this comment, it just explain
Alan Li 2015/11/18 17:07:03 Done.
1278 mfc1(t8, fs);
1279 Cvt_d_uw(fd, t8, scratch, fs);
1280 }
1276 } 1281 }
1277 1282
1278 1283
1279 void MacroAssembler::Cvt_d_uw(FPURegister fd, 1284 void MacroAssembler::Cvt_d_uw(FPURegister fd, Register rs, FPURegister scratch,
1280 Register rs, 1285 FPURegister fs) {
1281 FPURegister scratch) {
1282 // Convert rs to a FP value in fd (and fd + 1). 1286 // Convert rs to a FP value in fd (and fd + 1).
1283 // We do this by converting rs minus the MSB to avoid sign conversion, 1287 // We do this by converting rs minus the MSB to avoid sign conversion,
1284 // then adding 2^31 to the result (if needed). 1288 // then adding 2^31 to the result (if needed).
paul.l... 2015/11/18 01:49:13 This comment block is stale, you changed the funct
Alan Li 2015/11/18 17:07:03 Done.
1285 1289
1286 DCHECK(!fd.is(scratch)); 1290 DCHECK(!fd.is(scratch));
1287 DCHECK(!rs.is(t9)); 1291 DCHECK(!rs.is(t9));
1288 DCHECK(!rs.is(at)); 1292 DCHECK(!rs.is(at));
1289 1293
1290 // Save rs's MSB to t9. 1294 Label msb_clear, conversion_done;
1291 Ext(t9, rs, 31, 1); 1295 Branch(&msb_clear, ge, rs, Operand(zero_reg));
paul.l... 2015/11/18 01:49:13 you can use delay slot here to save an instruction
Alan Li 2015/11/18 17:07:03 Done.
1292 // Remove rs's MSB.
1293 Ext(at, rs, 0, 31);
1294 // Move the result to fd.
1295 mtc1(at, fd);
1296 1296
1297 // Convert fd to a real FP value. 1297 li(at, 0x41f00000);
paul.l... 2015/11/18 01:49:13 This should have a comment, about FP value of 2^32
Alan Li 2015/11/18 17:07:03 Done.
1298 cvt_d_w(fd, fd);
1299
1300 Label conversion_done;
1301
1302 // If rs's MSB was 0, it's done.
1303 // Otherwise we need to add that to the FP register.
1304 Branch(&conversion_done, eq, t9, Operand(zero_reg));
1305
1306 // Load 2^31 into f20 as its float representation.
1307 li(at, 0x41E00000);
1308 mtc1(zero_reg, scratch); 1298 mtc1(zero_reg, scratch);
1309 Mthc1(at, scratch); 1299 Mthc1(at, scratch);
1310 // Add it to fd. 1300
1301 if (fs.is(no_freg)) {
1302 mtc1(rs, fd);
1303 cvt_d_w(fd, fd);
1304 } else {
1305 cvt_d_w(fd, fs);
1306 }
1307
1308 Branch(USE_DELAY_SLOT, &conversion_done);
1311 add_d(fd, fd, scratch); 1309 add_d(fd, fd, scratch);
paul.l... 2015/11/18 01:49:13 Nice use of delay slot!
Alan Li 2015/11/18 17:07:03 Acknowledged.
1312 1310
1311 bind(&msb_clear);
1312 if (fs.is(no_freg)) {
1313 mtc1(rs, fd);
1314 cvt_d_w(fd, fd);
1315 } else {
1316 cvt_d_w(fd, fs);
1317 }
1318
1313 bind(&conversion_done); 1319 bind(&conversion_done);
1314 } 1320 }
1315 1321
1316 1322
1317 void MacroAssembler::Trunc_uw_d(FPURegister fd, 1323 void MacroAssembler::Trunc_uw_d(FPURegister fd,
1318 FPURegister fs, 1324 FPURegister fs,
1319 FPURegister scratch) { 1325 FPURegister scratch) {
1320 Trunc_uw_d(fs, t8, scratch); 1326 Trunc_uw_d(fs, t8, scratch);
1321 mtc1(t8, fd); 1327 mtc1(t8, fd);
1322 } 1328 }
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5854 if (mag.shift > 0) sra(result, result, mag.shift); 5860 if (mag.shift > 0) sra(result, result, mag.shift);
5855 srl(at, dividend, 31); 5861 srl(at, dividend, 31);
5856 Addu(result, result, Operand(at)); 5862 Addu(result, result, Operand(at));
5857 } 5863 }
5858 5864
5859 5865
5860 } // namespace internal 5866 } // namespace internal
5861 } // namespace v8 5867 } // namespace v8
5862 5868
5863 #endif // V8_TARGET_ARCH_MIPS 5869 #endif // V8_TARGET_ARCH_MIPS
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