Add BL (immediate) and BLX (register) to ARM assembler.

src/IceAssemblerARM32.cpp

Index: src/IceAssemblerARM32.cpp
diff --git a/src/IceAssemblerARM32.cpp b/src/IceAssemblerARM32.cpp
index 18996719f0aba27d121e32720a669741c93d0595..a428664714748b7bacde22aa3e4a1ca2b1ad68fd 100644
--- a/src/IceAssemblerARM32.cpp
+++ b/src/IceAssemblerARM32.cpp
@@ -327,6 +327,27 @@ MoveRelocatableFixup *AssemblerARM32::createMoveFixup(bool IsMovW,
   return F;
 }
 
+size_t BlRelocatableFixup::emit(GlobalContext *Ctx,
+                                const Assembler &Asm) const {
+  if (!BuildDefs::dump())
+    return InstARM32::InstSize;
+  Ostream &Str = Ctx->getStrEmit();
+  IValueT Inst = Asm.load<IValueT>(position());
+  Str << "\tbl\t" << symbol(Ctx) << "\t@ .word "
+      << llvm::format_hex_no_prefix(Inst, 8) << "\n";
+  return InstARM32::InstSize;
+}
+
+BlRelocatableFixup *
+AssemblerARM32::createBlFixup(const ConstantRelocatable *Target) {
+  BlRelocatableFixup *F =
+      new (allocate<BlRelocatableFixup>()) BlRelocatableFixup();

[John, 2015/11/18 01:04:17]

The usual idiom is to have a static create method in BlRelocatableFixup that
takes a Cfg, and returns a newly allocated object.

[Karl, 2015/11/18 16:19:37]

I was following the pattern for (all) other fixups. The create methods are in
the assembler class, not the fixup class.

Also, not sure where Cfg would come from since the fixups are generated in the
assembler, and assembler is designed to NOT require a Cfg. Note that the
assembler has it's own allocator, and that is the allocator we are using.

+  F->set_kind(llvm::ELF::R_ARM_CALL);
+  F->set_value(Target);
+  Buffer.installFixup(F);
+  return F;
+}
+
 void AssemblerARM32::bindCfgNodeLabel(const CfgNode *Node) {
   GlobalContext *Ctx = Node->getCfg()->getContext();
   if (BuildDefs::dump() && !Ctx->getFlags().getDisableHybridAssembly()) {
@@ -686,6 +707,38 @@ void AssemblerARM32::bic(const Operand *OpRd, const Operand *OpRn,
   emitType01(Opcode, OpRd, OpRn, OpSrc1, SetFlags, Cond);
 }
 
+void AssemblerARM32::bl(const ConstantRelocatable *Target) {
+  // BL (immediate) - ARM section A8.8.25, encoding A1:
+  //   bl<c> <label>
+  //
+  // cccc1011iiiiiiiiiiiiiiiiiiiiiiii where cccc=Cond (not currently allowed)
+  // and iiiiiiiiiiiiiiiiiiiiiiii is the (encoded) Target to branch to.
+  emitFixup(createBlFixup(Target));
+  constexpr CondARM32::Cond Cond = CondARM32::AL;
+  constexpr IValueT Immed = 0;
+  constexpr bool Link = true;
+  emitType05(Cond, Immed, Link);
+}
+
+void AssemblerARM32::blx(const Operand *Target) {
+  IValueT Rm;
+  if (decodeOperand(Target, Rm) != DecodedAsRegister)
+    return setNeedsTextFixup();
+  // BLX (register) - ARM section A8.8.26, encoding A1:
+  //   blx<c> <Rm>
+  //
+  // cccc000100101111111111110011mmmm where cccc=Cond (not currently allowed)
+  // and mmmm=Rm.
+  if (Rm == RegARM32::Encoded_Reg_pc)
+    // Unpredictable.
+    return setNeedsTextFixup();
+  AssemblerBuffer::EnsureCapacity ensured(&Buffer);
+  constexpr CondARM32::Cond Cond = CondARM32::AL;
+  int32_t Encoding = (static_cast<int32_t>(Cond) << kConditionShift) | B24 |
+                     B21 | (0xfff << 8) | B5 | B4 | (Rm << kRmShift);
+  emitInst(Encoding);
+}
+
 void AssemblerARM32::bx(RegARM32::GPRRegister Rm, CondARM32::Cond Cond) {
   // BX - ARM section A8.8.27, encoding A1:
   //   bx<c> <Rm>