Add BL (immediate) and BLX (register) to ARM assembler.

src/IceAssemblerARM32.cpp

 //===- subzero/src/IceAssemblerARM32.cpp - Assembler for ARM32 --*- C++ -*-===//
 //
 // Copyright (c) 2013, the Dart project authors.  Please see the AUTHORS file
 // for details. All rights reserved. Use of this source code is governed by a
 // BSD-style license that can be found in the LICENSE file.
 //
 // Modified by the Subzero authors.
 //
 //===----------------------------------------------------------------------===//
 //
@@ skipping 309 matching lines @@
                                                       const Constant *Value) {
   MoveRelocatableFixup *F =
       new (allocate<MoveRelocatableFixup>()) MoveRelocatableFixup();
   F->set_kind(IsMovW ? llvm::ELF::R_ARM_MOVW_ABS_NC
                      : llvm::ELF::R_ARM_MOVT_ABS);
   F->set_value(Value);
   Buffer.installFixup(F);
   return F;
 }
 
+size_t BlRelocatableFixup::emit(GlobalContext *Ctx,
+                                const Assembler &Asm) const {
+  if (!BuildDefs::dump())
+    return InstARM32::InstSize;
+  Ostream &Str = Ctx->getStrEmit();
+  IValueT Inst = Asm.load<IValueT>(position());
+  Str << "\tbl\t" << symbol(Ctx) << "\t@ .word "
+      << llvm::format_hex_no_prefix(Inst, 8) << "\n";
+  return InstARM32::InstSize;
+}
+
+BlRelocatableFixup *
+AssemblerARM32::createBlFixup(const ConstantRelocatable *Target) {
+  BlRelocatableFixup *F =
+      new (allocate<BlRelocatableFixup>()) BlRelocatableFixup();

[John, 2015/11/18 01:04:17]

The usual idiom is to have a static create method in BlRelocatableFixup that
takes a Cfg, and returns a newly allocated object.

[Karl, 2015/11/18 16:19:37]

I was following the pattern for (all) other fixups. The create methods are in
the assembler class, not the fixup class.

Also, not sure where Cfg would come from since the fixups are generated in the
assembler, and assembler is designed to NOT require a Cfg. Note that the
assembler has it's own allocator, and that is the allocator we are using.

+  F->set_kind(llvm::ELF::R_ARM_CALL);
+  F->set_value(Target);
+  Buffer.installFixup(F);
+  return F;
+}
+
 void AssemblerARM32::bindCfgNodeLabel(const CfgNode *Node) {
   GlobalContext *Ctx = Node->getCfg()->getContext();
   if (BuildDefs::dump() && !Ctx->getFlags().getDisableHybridAssembly()) {
     // Generate label name so that branches can find it.
     constexpr SizeT InstSize = 0;
     emitTextInst(Node->getAsmName() + ":", InstSize);
   }
   SizeT NodeNumber = Node->getIndex();
   assert(!getPreliminary());
   Label *L = getOrCreateCfgNodeLabel(NodeNumber);
@@ skipping 339 matching lines @@
   //
   // BIC (immediate) - ARM section A8.8.21, encoding A1:
   //   bic{s}<c> <Rd>, <Rn>, #<RotatedImm8>
   //
   // cccc0011110snnnnddddiiiiiiiiiiii where cccc=Cond, dddd=Rn, nnnn=Rn,
   // s=SetFlags, and iiiiiiiiiiii=Src1Value defining RotatedImm8.
   IValueT Opcode = B3 | B2 | B1; // i.e. 1110
   emitType01(Opcode, OpRd, OpRn, OpSrc1, SetFlags, Cond);
 }
 
+void AssemblerARM32::bl(const ConstantRelocatable *Target) {
+  // BL (immediate) - ARM section A8.8.25, encoding A1:
+  //   bl<c> <label>
+  //
+  // cccc1011iiiiiiiiiiiiiiiiiiiiiiii where cccc=Cond (not currently allowed)
+  // and iiiiiiiiiiiiiiiiiiiiiiii is the (encoded) Target to branch to.
+  emitFixup(createBlFixup(Target));
+  constexpr CondARM32::Cond Cond = CondARM32::AL;
+  constexpr IValueT Immed = 0;
+  constexpr bool Link = true;
+  emitType05(Cond, Immed, Link);
+}
+
+void AssemblerARM32::blx(const Operand *Target) {
+  IValueT Rm;
+  if (decodeOperand(Target, Rm) != DecodedAsRegister)
+    return setNeedsTextFixup();
+  // BLX (register) - ARM section A8.8.26, encoding A1:
+  //   blx<c> <Rm>
+  //
+  // cccc000100101111111111110011mmmm where cccc=Cond (not currently allowed)
+  // and mmmm=Rm.
+  if (Rm == RegARM32::Encoded_Reg_pc)
+    // Unpredictable.
+    return setNeedsTextFixup();
+  AssemblerBuffer::EnsureCapacity ensured(&Buffer);
+  constexpr CondARM32::Cond Cond = CondARM32::AL;
+  int32_t Encoding = (static_cast<int32_t>(Cond) << kConditionShift) | B24 |
+                     B21 | (0xfff << 8) | B5 | B4 | (Rm << kRmShift);
+  emitInst(Encoding);
+}
+
 void AssemblerARM32::bx(RegARM32::GPRRegister Rm, CondARM32::Cond Cond) {
   // BX - ARM section A8.8.27, encoding A1:
   //   bx<c> <Rm>
   //
   // cccc000100101111111111110001mmmm where mmmm=rm and cccc=Cond.
   if (!(isGPRRegisterDefined(Rm) && isConditionDefined(Cond)))
     return setNeedsTextFixup();
   AssemblerBuffer::EnsureCapacity ensured(&Buffer);
   const IValueT Encoding = (encodeCondition(Cond) << kConditionShift) | B24 |
                            B21 | (0xfff << 8) | B4 |
@@ skipping 543 matching lines @@
     // rr defined (RotationValue) rotate.
     constexpr IValueT Opcode = B26 | B25 | B23 | B22 | B21 | B20;
     emitUxt(Cond, Opcode, Rd, Rn, Rm, Rotation);
     return;
   }
   }
 }
 
 } // end of namespace ARM32
 } // end of namespace Ice