Subzero. ARM32. Introduces the ShAmtImm Operand.

src/IceTargetLoweringARM32.cpp

 //===- subzero/src/IceTargetLoweringARM32.cpp - ARM32 lowering ------------===//
 //
 //                        The Subzero Code Generator
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 ///
 /// \file
@@ skipping 1282 matching lines @@
 
 void TargetARM32::div0Check(Type Ty, Operand *SrcLo, Operand *SrcHi) {
   if (isGuaranteedNonzeroInt(SrcLo) || isGuaranteedNonzeroInt(SrcHi))
     return;
   Variable *SrcLoReg = legalizeToReg(SrcLo);
   switch (Ty) {
   default:
     llvm::report_fatal_error("Unexpected type");
   case IceType_i8:
   case IceType_i16: {
-    Operand *ShAmtF =
-        legalize(Ctx->getConstantInt32(32 - getScalarIntBitWidth(Ty)),
-                 Legal_Reg | Legal_Flex);
+    Operand *ShAmtImm = shAmtImm(32 - getScalarIntBitWidth(Ty));
     Variable *T = makeReg(IceType_i32);
-    _lsls(T, SrcLoReg, ShAmtF);
+    _lsls(T, SrcLoReg, ShAmtImm);
     Context.insert(InstFakeUse::create(Func, T));
   } break;
   case IceType_i32: {
     _tst(SrcLoReg, SrcLoReg);
     break;
   }
   case IceType_i64: {
     Variable *T = makeReg(IceType_i32);
     _orrs(T, SrcLoReg, legalize(SrcHi, Legal_Reg | Legal_Flex));
     // T isn't going to be used, but we need the side-effect of setting flags
@@ skipping 129 matching lines @@
   }
 
   Operand *src1RF(TargetARM32 *Target) const {
     return legalizeToRegOrFlex(Target, Src1);
   }
 
   Variable *unswappedSrc1R(TargetARM32 *Target) const {
     return legalizeToReg(Target, Swapped ? Src0 : Src1);
   }
 
-  Operand *unswappedSrc1RF(TargetARM32 *Target) const {
-    return legalizeToRegOrFlex(Target, Swapped ? Src0 : Src1);
-  }
-
 protected:
   Operand *const Src0;
   Operand *const Src1;
   const bool Swapped;
 
   static Variable *legalizeToReg(TargetARM32 *Target, Operand *Src) {
     return Target->legalizeToReg(Src);
   }
 
   static Operand *legalizeToRegOrFlex(TargetARM32 *Target, Operand *Src) {
@@ skipping 44 matching lines @@
 using DoubleOperands = NumericOperands<ConstantDouble>;
 
 class Int32Operands : public NumericOperands<ConstantInteger32> {
   Int32Operands() = delete;
   Int32Operands(const Int32Operands &) = delete;
   Int32Operands &operator=(const Int32Operands &) = delete;
 
 public:
   Int32Operands(Operand *S0, Operand *S1) : NumericOperands(S0, S1) {}
 
+  Operand *unswappedSrc1RShAmtImm(TargetARM32 *Target) const {
+    if (!swappedOperands() && hasConstOperand()) {
+      return Target->shAmtImm(getConstantValue() & 0x1F);
+    }
+    return legalizeToReg(Target, Swapped ? Src0 : Src1);
+  }
+
   bool immediateIsFlexEncodable() const {
     uint32_t Rotate, Imm8;
     return OperandARM32FlexImm::canHoldImm(getConstantValue(), &Rotate, &Imm8);
   }
 
   bool negatedImmediateIsFlexEncodable() const {
     uint32_t Rotate, Imm8;
     return OperandARM32FlexImm::canHoldImm(
         -static_cast<int32_t>(getConstantValue()), &Rotate, &Imm8);
   }
@@ skipping 196 matching lines @@
       if (ShAmtImm == 0) {
         _mov(DestLo, Src0RLo);
         _mov(DestHi, SrcsHi.src0R(this));
         return;
       }
 
       if (ShAmtImm >= 32) {
         if (ShAmtImm == 32) {
           _mov(DestHi, Src0RLo);
         } else {
-          Operand *ShAmtOp = legalize(Ctx->getConstantInt32(ShAmtImm - 32),
-                                      Legal_Reg | Legal_Flex);
+          Operand *ShAmtOp = shAmtImm(ShAmtImm - 32);
           _lsl(T_Hi, Src0RLo, ShAmtOp);
           _mov(DestHi, T_Hi);
         }
 
         Operand *_0 =
             legalize(Ctx->getConstantZero(IceType_i32), Legal_Reg | Legal_Flex);
         _mov(T_Lo, _0);
         _mov(DestLo, T_Lo);
         return;
       }
 
       Variable *Src0RHi = SrcsHi.src0R(this);
-      Operand *ShAmtOp =
-          legalize(Ctx->getConstantInt32(ShAmtImm), Legal_Reg | Legal_Flex);
-      Operand *ComplShAmtOp = legalize(Ctx->getConstantInt32(32 - ShAmtImm),
-                                       Legal_Reg | Legal_Flex);
+      Operand *ShAmtOp = shAmtImm(ShAmtImm);
+      Operand *ComplShAmtOp = shAmtImm(32 - ShAmtImm);
       _lsl(T_Hi, Src0RHi, ShAmtOp);
       _orr(T_Hi, T_Hi,
            OperandARM32FlexReg::create(Func, IceType_i32, Src0RLo,
                                        OperandARM32::LSR, ComplShAmtOp));
       _mov(DestHi, T_Hi);
 
       _lsl(T_Lo, Src0RLo, ShAmtOp);
       _mov(DestLo, T_Lo);
       return;
     }
@@ skipping 52 matching lines @@
     _mov(DestLo, TA_Lo);
     _mov(DestHi, TA_Hi);
     return;
   }
   case InstArithmetic::Lshr:
   case InstArithmetic::Ashr: {
     const bool ASR = Op == InstArithmetic::Ashr;
     if (!SrcsLo.swappedOperands() && SrcsLo.hasConstOperand()) {
       Variable *Src0RHi = SrcsHi.src0R(this);
       // Truncating the ShAmt to [0, 63] because that's what ARM does anyway.
-      const int32_t ShAmtImm = SrcsLo.getConstantValue() & 0x3F;
-      if (ShAmtImm == 0) {
+      const int32_t ShAmt = SrcsLo.getConstantValue() & 0x3F;
+      if (ShAmt == 0) {
         _mov(DestHi, Src0RHi);
         _mov(DestLo, SrcsLo.src0R(this));
         return;
       }
 
-      if (ShAmtImm >= 32) {
-        if (ShAmtImm == 32) {
+      if (ShAmt >= 32) {
+        if (ShAmt == 32) {
           _mov(DestLo, Src0RHi);
         } else {
-          Operand *ShAmtOp = legalize(Ctx->getConstantInt32(ShAmtImm - 32),
-                                      Legal_Reg | Legal_Flex);
+          Operand *ShAmtImm = shAmtImm(ShAmt - 32);
           if (ASR) {
-            _asr(T_Lo, Src0RHi, ShAmtOp);
+            _asr(T_Lo, Src0RHi, ShAmtImm);
           } else {
-            _lsr(T_Lo, Src0RHi, ShAmtOp);
+            _lsr(T_Lo, Src0RHi, ShAmtImm);
           }
           _mov(DestLo, T_Lo);
         }
 
         if (ASR) {
-          Operand *_31 = legalize(Ctx->getConstantZero(IceType_i32),
-                                  Legal_Reg | Legal_Flex);
+          Operand *_31 = shAmtImm(31);
           _asr(T_Hi, Src0RHi, _31);
         } else {
           Operand *_0 = legalize(Ctx->getConstantZero(IceType_i32),
                                  Legal_Reg | Legal_Flex);
           _mov(T_Hi, _0);
         }
         _mov(DestHi, T_Hi);
         return;
       }
 
       Variable *Src0RLo = SrcsLo.src0R(this);
-      Operand *ShAmtOp =
-          legalize(Ctx->getConstantInt32(ShAmtImm), Legal_Reg | Legal_Flex);
-      Operand *ComplShAmtOp = legalize(Ctx->getConstantInt32(32 - ShAmtImm),
-                                       Legal_Reg | Legal_Flex);
-      _lsr(T_Lo, Src0RLo, ShAmtOp);
+      Operand *ShAmtImm = shAmtImm(ShAmt);
+      Operand *ComplShAmtImm = shAmtImm(32 - ShAmt);
+      _lsr(T_Lo, Src0RLo, ShAmtImm);
       _orr(T_Lo, T_Lo,
            OperandARM32FlexReg::create(Func, IceType_i32, Src0RHi,
-                                       OperandARM32::LSL, ComplShAmtOp));
+                                       OperandARM32::LSL, ComplShAmtImm));
       _mov(DestLo, T_Lo);
 
       if (ASR) {
-        _asr(T_Hi, Src0RHi, ShAmtOp);
+        _asr(T_Hi, Src0RHi, ShAmtImm);
       } else {
-        _lsr(T_Hi, Src0RHi, ShAmtOp);
+        _lsr(T_Hi, Src0RHi, ShAmtImm);
       }
       _mov(DestHi, T_Hi);
       return;
     }
 
     // a=b>>c
     // pnacl-llc does:
     // mov        t_b.lo, b.lo
     // mov        t_b.hi, b.hi
     // mov        t_c.lo, c.lo
@@ skipping 254 matching lines @@
   }
   case InstArithmetic::Mul: {
     Variable *Src0R = Srcs.unswappedSrc0R(this);
     Variable *Src1R = Srcs.unswappedSrc1R(this);
     _mul(T, Src0R, Src1R);
     _mov(Dest, T);
     return;
   }
   case InstArithmetic::Shl: {
     Variable *Src0R = Srcs.unswappedSrc0R(this);
-    Operand *Src1R = Srcs.unswappedSrc1RF(this);
+    Operand *Src1R = Srcs.unswappedSrc1RShAmtImm(this);
     _lsl(T, Src0R, Src1R);
     _mov(Dest, T);
     return;
   }
   case InstArithmetic::Lshr: {
     Variable *Src0R = Srcs.unswappedSrc0R(this);
     if (Dest->getType() != IceType_i32) {
       _uxt(Src0R, Src0R);
     }
-    _lsr(T, Src0R, Srcs.unswappedSrc1RF(this));
+    _lsr(T, Src0R, Srcs.unswappedSrc1RShAmtImm(this));
     _mov(Dest, T);
     return;
   }
   case InstArithmetic::Ashr: {
     Variable *Src0R = Srcs.unswappedSrc0R(this);
     if (Dest->getType() != IceType_i32) {
       _sxt(Src0R, Src0R);
     }
-    _asr(T, Src0R, Srcs.unswappedSrc1RF(this));
+    _asr(T, Src0R, Srcs.unswappedSrc1RShAmtImm(this));
     _mov(Dest, T);
     return;
   }
   case InstArithmetic::Udiv:
   case InstArithmetic::Sdiv:
   case InstArithmetic::Urem:
   case InstArithmetic::Srem:
     llvm::report_fatal_error(
         "Integer div/rem should have been handled earlier.");
     return;
@@ skipping 994 matching lines @@
 
 TargetARM32::CondWhenTrue
 TargetARM32::lowerInt8AndInt16IcmpCond(InstIcmp::ICond Condition, Operand *Src0,
                                        Operand *Src1) {
   Int32Operands Srcs(Src0, Src1);
   const int32_t ShAmt = 32 - getScalarIntBitWidth(Src0->getType());
   assert(ShAmt >= 0);
 
   if (!Srcs.hasConstOperand()) {
     Variable *Src0R = makeReg(IceType_i32);
-    Operand *ShAmtF =
-        legalize(Ctx->getConstantInt32(ShAmt), Legal_Reg | Legal_Flex);
-    _lsl(Src0R, legalizeToReg(Src0), ShAmtF);
+    Operand *ShAmtImm = shAmtImm(ShAmt);
+    _lsl(Src0R, legalizeToReg(Src0), ShAmtImm);
 
     Variable *Src1R = legalizeToReg(Src1);
     OperandARM32FlexReg *Src1F = OperandARM32FlexReg::create(
-        Func, IceType_i32, Src1R, OperandARM32::LSL, ShAmtF);
+        Func, IceType_i32, Src1R, OperandARM32::LSL, ShAmtImm);
     _cmp(Src0R, Src1F);
     return CondWhenTrue(getIcmp32Mapping(Condition));
   }
 
   const int32_t Value = Srcs.getConstantValue();
   if ((Condition == InstIcmp::Eq || Condition == InstIcmp::Ne) && Value == 0) {
-    Operand *ShAmtOp = Ctx->getConstantInt32(ShAmt);
+    Operand *ShAmtImm = shAmtImm(ShAmt);
     Variable *T = makeReg(IceType_i32);
-    _lsls(T, Srcs.src0R(this), ShAmtOp);
+    _lsls(T, Srcs.src0R(this), ShAmtImm);
     Context.insert(InstFakeUse::create(Func, T));
     return CondWhenTrue(getIcmp32Mapping(Condition));
   }
 
   Variable *ConstR = makeReg(IceType_i32);
   _mov(ConstR,
        legalize(Ctx->getConstantInt32(Value << ShAmt), Legal_Reg | Legal_Flex));
   Operand *NonConstF = OperandARM32FlexReg::create(
       Func, IceType_i32, Srcs.src0R(this), OperandARM32::LSL,
       Ctx->getConstantInt32(ShAmt));
@@ skipping 556 matching lines @@
       _rev(T_Lo, Val_Lo);
       _rev(T_Hi, Val_Hi);
       _mov(DestLo, T_Hi);
       _mov(DestHi, T_Lo);
     } else {
       assert(Ty == IceType_i32 || Ty == IceType_i16);
       Variable *ValR = legalizeToReg(Val);
       Variable *T = makeReg(Ty);
       _rev(T, ValR);
       if (Val->getType() == IceType_i16) {
-        Operand *Sixteen =
-            legalize(Ctx->getConstantInt32(16), Legal_Reg | Legal_Flex);
-        _lsr(T, T, Sixteen);
+        Operand *_16 = shAmtImm(16);
+        _lsr(T, T, _16);
       }
       _mov(Dest, T);
     }
     return;
   }
   case Intrinsics::Ctpop: {
     Operand *Val = Instr->getArg(0);
     InstCall *Call = makeHelperCall(isInt32Asserting32Or64(Val->getType())
                                         ? H_call_ctpop_i32
                                         : H_call_ctpop_i64,
@@ skipping 773 matching lines @@
     return;
   }
 
   Variable *Src0Var = legalizeToReg(Src0);
   // If Src0 is not an i32, we left shift it -- see the icmp lowering for the
   // reason.
   assert(Src0Var->mustHaveReg());
   const size_t ShiftAmt = 32 - getScalarIntBitWidth(Src0->getType());
   assert(ShiftAmt < 32);
   if (ShiftAmt > 0) {
-    Operand *ShiftConst = Ctx->getConstantInt32(ShiftAmt);
+    Operand *ShAmtImm = shAmtImm(ShiftAmt);
     Variable *T = makeReg(IceType_i32);
-    _lsl(T, Src0Var, ShiftConst);
+    _lsl(T, Src0Var, ShAmtImm);
     Src0Var = T;
   }
 
   for (SizeT I = 0; I < NumCases; ++I) {
     Operand *Value = Ctx->getConstantInt32(Inst->getValue(I) << ShiftAmt);
     Value = legalize(Value, Legal_Reg | Legal_Flex);
     _cmp(Src0Var, Value);
     _br(Inst->getLabel(I), CondARM32::EQ);
   }
   _br(Inst->getLabelDefault());
@@ skipping 831 matching lines @@
   // Technically R9 is used for TLS with Sandboxing, and we reserve it.
   // However, for compatibility with current NaCl LLVM, don't claim that.
   Str << ".eabi_attribute 14, 3   @ Tag_ABI_PCS_R9_use: Not used\n";
 }
 
 llvm::SmallBitVector TargetARM32::TypeToRegisterSet[IceType_NUM];
 llvm::SmallBitVector TargetARM32::RegisterAliases[RegARM32::Reg_NUM];
 llvm::SmallBitVector TargetARM32::ScratchRegs;
 
 } // end of namespace Ice