Subzero. ARM32. Introduces the ShAmtImm Operand.

src/IceInstARM32.h

 //===- subzero/src/IceInstARM32.h - ARM32 machine instructions --*- C++ -*-===//
 //
 //                        The Subzero Code Generator
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 ///
 /// \file
@@ skipping 20 matching lines @@
 /// OperandARM32Mem and OperandARM32Flex.
 class OperandARM32 : public Operand {
   OperandARM32() = delete;
   OperandARM32(const OperandARM32 &) = delete;
   OperandARM32 &operator=(const OperandARM32 &) = delete;
 
 public:
   enum OperandKindARM32 {
     k__Start = Operand::kTarget,
     kMem,
+    kShAmtImm,
     kFlexStart,
     kFlexImm = kFlexStart,
     kFlexFpImm,
     kFlexFpZero,
     kFlexReg,
     kFlexEnd = kFlexReg
   };
 
   enum ShiftKind {
     kNoShift = -1,
@@ skipping 94 matching lines @@
                   ShiftKind ShiftOp, uint16_t ShiftAmt, AddrMode Mode);
 
   Variable *Base;
   ConstantInteger32 *ImmOffset;
   Variable *Index;
   ShiftKind ShiftOp;
   uint16_t ShiftAmt;
   AddrMode Mode;
 };
 
+/// OperandARM32ShAmtImm represents an Immediate that is used in one of the
+/// shift-by-immediate instructions (lsl, lsr, and asr), and shift-by-immediate
+/// shifted registers.
+class OperandARM32ShAmtImm : public OperandARM32 {
+  OperandARM32ShAmtImm() = delete;
+  OperandARM32ShAmtImm(const OperandARM32ShAmtImm &) = delete;
+  OperandARM32ShAmtImm &operator=(const OperandARM32ShAmtImm &) = delete;
+
+public:
+  static OperandARM32ShAmtImm *create(Cfg *Func, ConstantInteger32 *ShAmt) {
+    return new (Func->allocate<OperandARM32ShAmtImm>())
+        OperandARM32ShAmtImm(ShAmt);
+  }
+
+  static bool classof(const Operand *Operand) {
+    return Operand->getKind() == static_cast<OperandKind>(kShAmtImm);
+  }
+
+  void emit(const Cfg *Func) const override;
+  using OperandARM32::dump;
+  void dump(const Cfg *Func, Ostream &Str) const override;
+
+  uint32_t getShAmtImm() const { return ShAmt->getValue(); }
+
+private:
+  explicit OperandARM32ShAmtImm(ConstantInteger32 *SA);
+
+  const ConstantInteger32 *const ShAmt;
+};
+
 /// OperandARM32Flex represent the "flexible second operand" for data-processing
 /// instructions. It can be a rotatable 8-bit constant, or a register with an
 /// optional shift operand. The shift amount can even be a third register.
 class OperandARM32Flex : public OperandARM32 {
   OperandARM32Flex() = delete;
   OperandARM32Flex(const OperandARM32Flex &) = delete;
   OperandARM32Flex &operator=(const OperandARM32Flex &) = delete;
 
 public:
   static bool classof(const Operand *Operand) {
@@ skipping 1150 matching lines @@
 // default implementations. Without this, there is the possibility of ODR
 // violations and link errors.
 
 template <> void InstARM32Ldr::emit(const Cfg *Func) const;
 template <> void InstARM32Movw::emit(const Cfg *Func) const;
 template <> void InstARM32Movt::emit(const Cfg *Func) const;
 
 } // end of namespace Ice
 
 #endif // SUBZERO_SRC_ICEINSTARM32_H