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Side by Side Diff: src/IceInstARM32.cpp

Issue 1449263003: Subzero. ARM32. Introduces the ShAmtImm Operand. (Closed) Base URL: https://chromium.googlesource.com/native_client/pnacl-subzero.git@master
Patch Set: Created 5 years, 1 month ago
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1 //===- subzero/src/IceInstARM32.cpp - ARM32 instruction implementation ----===// 1 //===- subzero/src/IceInstARM32.cpp - ARM32 instruction implementation ----===//
2 // 2 //
3 // The Subzero Code Generator 3 // The Subzero Code Generator
4 // 4 //
5 // This file is distributed under the University of Illinois Open Source 5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details. 6 // License. See LICENSE.TXT for details.
7 // 7 //
8 //===----------------------------------------------------------------------===// 8 //===----------------------------------------------------------------------===//
9 /// 9 ///
10 /// \file 10 /// \file
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240 Variable *Index, ShiftKind ShiftOp, 240 Variable *Index, ShiftKind ShiftOp,
241 uint16_t ShiftAmt, AddrMode Mode) 241 uint16_t ShiftAmt, AddrMode Mode)
242 : OperandARM32(kMem, Ty), Base(Base), ImmOffset(0), Index(Index), 242 : OperandARM32(kMem, Ty), Base(Base), ImmOffset(0), Index(Index),
243 ShiftOp(ShiftOp), ShiftAmt(ShiftAmt), Mode(Mode) { 243 ShiftOp(ShiftOp), ShiftAmt(ShiftAmt), Mode(Mode) {
244 NumVars = 2; 244 NumVars = 2;
245 Vars = Func->allocateArrayOf<Variable *>(2); 245 Vars = Func->allocateArrayOf<Variable *>(2);
246 Vars[0] = Base; 246 Vars[0] = Base;
247 Vars[1] = Index; 247 Vars[1] = Index;
248 } 248 }
249 249
250 OperandARM32ShAmtImm::OperandARM32ShAmtImm(ConstantInteger32 *SA)
251 : OperandARM32(kShAmtImm, IceType_i8), ShAmt(SA) {}
252
250 bool OperandARM32Mem::canHoldOffset(Type Ty, bool SignExt, int32_t Offset) { 253 bool OperandARM32Mem::canHoldOffset(Type Ty, bool SignExt, int32_t Offset) {
251 int32_t Bits = SignExt ? TypeARM32Attributes[Ty].SExtAddrOffsetBits 254 int32_t Bits = SignExt ? TypeARM32Attributes[Ty].SExtAddrOffsetBits
252 : TypeARM32Attributes[Ty].ZExtAddrOffsetBits; 255 : TypeARM32Attributes[Ty].ZExtAddrOffsetBits;
253 if (Bits == 0) 256 if (Bits == 0)
254 return Offset == 0; 257 return Offset == 0;
255 // Note that encodings for offsets are sign-magnitude for ARM, so we check 258 // Note that encodings for offsets are sign-magnitude for ARM, so we check
256 // with IsAbsoluteUint(). 259 // with IsAbsoluteUint().
257 return Utils::IsAbsoluteUint(Bits, Offset); 260 return Utils::IsAbsoluteUint(Bits, Offset);
258 } 261 }
259 262
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1764 if (getShiftOp() != kNoShift) { 1767 if (getShiftOp() != kNoShift) {
1765 Str << ", " << InstARM32ShiftAttributes[getShiftOp()].EmitString << " #" 1768 Str << ", " << InstARM32ShiftAttributes[getShiftOp()].EmitString << " #"
1766 << getShiftAmt(); 1769 << getShiftAmt();
1767 } 1770 }
1768 } else { 1771 } else {
1769 getOffset()->dump(Func, Str); 1772 getOffset()->dump(Func, Str);
1770 } 1773 }
1771 Str << "] AddrMode==" << getAddrMode(); 1774 Str << "] AddrMode==" << getAddrMode();
1772 } 1775 }
1773 1776
1777 void OperandARM32ShAmtImm::emit(const Cfg *Func) const { ShAmt->emit(Func); }
1778
1779 void OperandARM32ShAmtImm::dump(const Cfg *, Ostream &Str) const {
1780 ShAmt->dump(Str);
1781 }
1782
1774 void OperandARM32FlexImm::emit(const Cfg *Func) const { 1783 void OperandARM32FlexImm::emit(const Cfg *Func) const {
1775 if (!BuildDefs::dump()) 1784 if (!BuildDefs::dump())
1776 return; 1785 return;
1777 Ostream &Str = Func->getContext()->getStrEmit(); 1786 Ostream &Str = Func->getContext()->getStrEmit();
1778 uint32_t Imm = getImm(); 1787 uint32_t Imm = getImm();
1779 uint32_t RotateAmt = getRotateAmt(); 1788 uint32_t RotateAmt = getRotateAmt();
1780 Str << "#" << Utils::rotateRight32(Imm, 2 * RotateAmt); 1789 Str << "#" << Utils::rotateRight32(Imm, 2 * RotateAmt);
1781 } 1790 }
1782 1791
1783 void OperandARM32FlexImm::dump(const Cfg * /* Func */, Ostream &Str) const { 1792 void OperandARM32FlexImm::dump(const Cfg * /* Func */, Ostream &Str) const {
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1916 template class InstARM32UnaryopFP<InstARM32::Vsqrt>; 1925 template class InstARM32UnaryopFP<InstARM32::Vsqrt>;
1917 1926
1918 template class InstARM32FourAddrGPR<InstARM32::Mla>; 1927 template class InstARM32FourAddrGPR<InstARM32::Mla>;
1919 template class InstARM32FourAddrGPR<InstARM32::Mls>; 1928 template class InstARM32FourAddrGPR<InstARM32::Mls>;
1920 1929
1921 template class InstARM32CmpLike<InstARM32::Cmn>; 1930 template class InstARM32CmpLike<InstARM32::Cmn>;
1922 template class InstARM32CmpLike<InstARM32::Cmp>; 1931 template class InstARM32CmpLike<InstARM32::Cmp>;
1923 template class InstARM32CmpLike<InstARM32::Tst>; 1932 template class InstARM32CmpLike<InstARM32::Tst>;
1924 1933
1925 } // end of namespace Ice 1934 } // end of namespace Ice
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